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12 lvpecl/24 cmos output clock generator ad9520-5 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008 analog devices, inc. all rights reserved. features low phase noise, phase-locked loop (pll) supports external 3.3 v/5 v vco/vcxo to 2.4 ghz 1 differential or 2 single-ended reference inputs accepts cmos, lvds, or lvpecl references to 250 mhz accepts 16.67 mhz to 33.3 mhz crystal for reference input optional reference clock doubler reference monitoring capability auto and manual reference switchover/holdover modes, with selectable revertive/nonrevertive switching glitch-free switchover between references automatic recovery from holdover digital or analog lock detect, selectable optional zero delay operation twelve 1.6 ghz lvpecl outputs divided into 4 groups each group of 3 has a 1-to-32 divider with phase delay additive output jitter as low as 225 fs rms channel-to-channel skew grouped outputs <16 ps each lvpecl output can be configured as 2 cmos outputs (for f out 250 mhz) automatic synchronization of all outputs on power-up manual synchronization of outputs as needed spi- and i2c-compatible serial control port 64-lead lfcsp nonvolatile eeprom stores configuration settings applications low jitter, low phase noise clock distribution clock generation and translation for sonet, 10ge, 10g fc, and other 10 gbps protocols forward error correction (g.710) clocking high speed adcs, dacs, ddss, ddcs, ducs, mxfes high performance wireless transceivers ate and high performance instrumentation broadband infrastructures general description the ad9520-5 1 provides a multioutput clock distribution function with subpicosecond jitter performance, along with an on-chip pll that can be used with an external vco. the ad9520 serial interface supports both spi and i2c? ports. an in-package eeprom can be programmed through the serial interface and store user-defined register settings for power-up and chip reset. functional block diagram ref1 ref2 clk switchover and monitor pll divider and muxes zero delay cp status monitor spi/i 2 c control port and digital logic eeprom ad9520-5 out0 out1 out2 div/ out3 out4 out5 div/ out6 out7 out8 div/ out9 out10 out11 div/ lvpecl/ cmos refin refin clk 07239-001 figure 1. the ad9520 features 12 lvpecl outputs in four groups. any of the 1.6 ghz lvpecl outputs can be reconfigured as two 250 mhz cmos outputs. each group of outputs has a divider that allows both the divide ratio (from 1 to 32) and the phase (coarse delay) to be set. the ad9520 is available in a 64-lead lfcsp and can be operated from a single 3.3 v supply. the external vco can have an operating voltage up to 5.5 v. a separate output driver power supply can be from 2.375 v to 3.465 v. the ad9520 is specified for operation over the standard industrial range of ?40c to +85c. 1 the ad9520 is used throughout this data sheet to refer to all the members of the ad9520 family. however, when ad9520-5 is used , it refers to that specific member of the ad9520 family.
ad9520-5 rev. 0 | page 2 of 80 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 3 specifications ..................................................................................... 4 power supply requirements ....................................................... 4 pll characteristics ...................................................................... 4 clock inputs .................................................................................. 7 clock outputs ............................................................................... 7 timing characteristics ................................................................ 8 timing diagrams ..................................................................... 9 clock output additive phase noise (distribution only; vco divider not used) ......................... 10 clock output absolute time jitter (clock generation using external vcxo) ............................ 11 clock output additive time jitter (vco divider not used) .......................................................... 11 clock output additive time jitter (vco divider used) ..... 12 serial control portspi mode ................................................ 12 serial control porti2c mode ................................................ 13 pd , sync , and reset pins ..................................................... 14 serial port setup pins: sp1, sp0 ............................................... 14 ld, status, and refmon pins ............................................ 14 power dissipation ....................................................................... 15 absolute maximum ratings .......................................................... 16 thermal resistance .................................................................... 16 esd caution ................................................................................ 16 pin configuration and function descriptions ........................... 17 typical performance characteristics ........................................... 20 terminology .................................................................................... 24 detailed block diagram ................................................................ 25 theory of operation ...................................................................... 26 operational configurations ...................................................... 26 mode 1: clock distribution or external vco < 1600 mhz .................................................. 26 mode 2: high frequency clock distribution clk or external vco > 1600 mhz .................................... 28 phase-locked loop (pll) .................................................... 30 configuration of the pll ...................................................... 30 phase frequency detector (pfd) ........................................ 30 charge pump (cp) ................................................................. 30 pll external loop filter ....................................................... 31 pll reference inputs ............................................................. 31 reference switchover ............................................................. 31 reference divider r ............................................................... 32 vco/vcxo feedback divider n: p, a, b, r ..................... 32 digital lock detect (dld) ................................................... 33 analog lock detect (ald) ................................................... 34 current source digital lock detect (csdld) .................. 34 external vcxo/vco clock input (clk/ clk ) ................ 34 holdover .................................................................................. 34 external/manual holdover mode ........................................ 35 automatic/internal holdover mode .................................... 35 frequency status monitors ................................................... 37 zero delay operation ................................................................ 38 clock distribution ..................................................................... 39 operation modes ................................................................... 39 clk direct-to-lvpecl outputs ......................................... 39 clock frequency division ..................................................... 40 vco divider ........................................................................... 40 channel dividers ................................................................... 40 synchronizing the outputs sync function ................... 42 lvpecl output drivers ....................................................... 43 cmos output drivers .......................................................... 44 reset modes ................................................................................ 44 power-on reset ...................................................................... 44 hardware reset via the reset pin ..................................... 44 soft reset via the serial port ................................................. 44 soft reset to settings in eeprom when eeprom pin = 0 via the serial port ..................................... 44 power-down modes .................................................................. 44 chip power-down via pd .................................................... 44 pll power-down ................................................................... 45 distribution power-down .................................................... 45 individual clock output power-down ............................... 45 individual clock channel power-down ............................. 45
ad9520-5 rev. 0 | page 3 of 80 serial control port .......................................................................... 46 spi/i2c port selection ................................................................ 46 i2c serial port operation ........................................................... 46 i 2 c bus characteristics ........................................................... 46 data transfer process ............................................................. 47 data transfer format ............................................................. 48 i2c serial port timing ............................................................ 48 spi serial port operation ........................................................... 49 pin descriptions ...................................................................... 49 spi mode operation ............................................................... 49 communication cycleinstruction plus data .................. 49 write ......................................................................................... 49 read .......................................................................................... 49 spi instruction word (16 bits) .................................................. 50 spi msb/lsb first transfers ..................................................... 50 eeprom operations ...................................................................... 53 writing to the eeprom ............................................................ 53 reading from the eeprom ...................................................... 53 programming the eeprom buffer segment.......................... 53 register section definition group ....................................... 54 io_update (operational code 0x80) .............................. 54 end-of-data (operational code 0xff) ............................... 54 pseudo-end-of-data (operational code 0xfe) ................. 54 thermal performance ..................................................................... 55 register map .................................................................................... 56 register map descriptions ............................................................. 61 applications information ............................................................... 75 frequency planning using the ad9520 .................................. 75 using the ad9520 outputs for adc clock applications .... 75 lvpecl clock distribution ...................................................... 75 cmos clock distribution ......................................................... 76 outline dimensions ........................................................................ 77 ordering guide ........................................................................... 77 revision history 10/08revision 0: initial version
ad9520-5 rev. 0 | page 4 of 80 specifications typical (typ) is given for vs = vs_drv = 3.3 v 5%; vs vcp 5.25 v; t a = 25c; rset = 4.12 k; cprset = 5.1 k, unless otherwise noted. minimum (min) and maximum (max) values are given over full vs and t a (?40c to +85c) variation. power supply requirements table 1. parameter min typ max unit test conditions/comments vs 3.135 3.3 3.465 v 3.3 v 5% vs_drv 2.375 vs v this is nominally 2.5 v to 3.3 v 5% vcp vs 5.25 v this is nominally 3.3 v to 5.0 v 5% rset pin resistor 4.12 k sets internal biasing currents; connect to ground cprset pin resistor 5.1 k sets internal cp current range, nominally 4.8 ma (cp_lsb = 600 a); actual current can be calculated by cp_lsb = 3.06/cprset; connect to ground pll characteristics table 2. parameter min typ max unit test conditions/comments reference inputs differential mode (refin, refin ) differential mode (can accommodate single-ended input by ac grounding undriven input) input frequency 0 250 mhz frequencies below about 1 mhz should be dc-coupled; be careful to match v cm (self-bias voltage) input sensitivity 280 mv p-p self-bias voltage, refin 1.34 1.60 1.75 v self-bias voltage of refin 1 self-bias voltage, refin 1.30 1.50 1.60 v self-bias voltage of refin 1 input resistance, refin 4.0 4.8 5.9 k self-biased 1 input resistance, refin 4.4 5.3 6.4 k self-biased 1 dual single-ended mode (ref1, ref2) two single-ended cmos-compatible inputs input frequency (ac-coupled) with dc offset off) 10 250 mhz slew rate must be > 50 v/s input frequency (ac-coupled with dc offset on) 250 mhz slew rate must be > 50 v/s, and input amplitude sensitivity specification must be met; see input sensitivity input frequency (dc-coupled) 0 250 mhz slew rate > 50 v/s; cmos levels input sensitivity (ac-coupled with dc offset off) 0.55 3.28 v p-p vih should not exceed vs input sensitivity (ac-coupled with dc offset on) 1.5 2.78 v p-p vih should not exceed vs input logic high, dc offset off 2.0 v input logic low, dc offset off 0.8 v input current ?100 +100 a input capacitance 2 pf each pin, refin (ref1)/ refin (ref2) crystal oscillator crystal resonator frequency range 16.67 33.33 mhz maximum crystal motional resistance 30 phase/frequency detector (pfd) pfd input frequency 100 mhz antibacklash pulse width = 1.3 ns, 2.9 ns 45 mhz antibacklash pulse width = 6.0 ns reference input clock doubler frequency 0.004 50 mhz antibacklash pulse width = 1.3 ns, 2.9 ns antibacklash pulse width 1.3 ns 0x017[1:0] = 01b 2.9 ns 0x017[1:0] = 00b; 0x017[1:0] = 11b 6.0 ns 0x017[1:0] = 10b
ad9520-5 rev. 0 | page 5 of 80 parameter min typ max unit test conditions/comments charge pump (cp) i cp sink/source programmable high value 4.8 ma with cprset = 5.1 k; higher i cp is possible by changing cprset low value 0.60 ma with cprset = 5.1 k; lower i cp is possible by changing cprset absolute accuracy 2.5 % charge pump voltage set to v cp /2 cprset range 2.7 10 k i cp high impedance mode leakage 1 na sink-and-source current matching 1 % 0.5 v < v cp < vcp ? 0.5 v; v cp is the voltage on the cp (charge pump) pin; vcp is the voltage on the vcp power supply pin i cp vs. v cp 1.5 % 0.5 v < v cp < vcp ? 0.5 v i cp vs. temperature 2 % v cp = vcp/2 v prescaler (part of n divider) prescaler input frequency p = 1 fd 300 mhz p = 2 fd 600 mhz p = 3 fd 900 mhz p = 2 dm (2/3) 600 mhz p = 4 dm (4/5) 1000 mhz p = 8 dm (8/9) 2400 mhz p = 16 dm (16/17) 3000 mhz p = 32 dm (32/33) 3000 mhz prescaler output frequency 300 mhz a, b counter input frequency (prescaler input frequency divided by p) pll n divider delay register 0x019[2:0]; see table 48 000 off 001 410 ps 010 530 ps 011 650 ps 100 770 ps 101 890 ps 110 1010 ps 111 1130 ps pll r divider delay register 0x019[5:3]; see table 48 000 off 001 370 ps 010 490 ps 011 610 ps 100 730 ps 101 850 ps 110 970 ps 111 1090 ps phase offset in zero delay ref refers to refin (ref1)/ refin (ref2) phase offset (ref-to-lvpecl clock output pins) in internal zero delay mode 560 1060 1310 ps when n delay and r delay are bypassed phase offset (ref-to-lvpecl clock output pins) in internal zero delay mode ?320 +50 +240 ps when n delay = setting 110 and r delay is bypassed
ad9520-5 rev. 0 | page 6 of 80 parameter min typ max unit test conditions/comments noise characteristics in-band phase noise of the charge pump/ phase frequency detector (in-band means within the lbw of the pll) the pll in-band phase noise floor is estimated by measuring the in-band phase noise at the output of the vco and subtracting 20 log(n) (where n is the value of the n divider) @ 500 khz pfd frequency ?165 dbc/hz @ 1 mhz pfd frequency ?162 dbc/hz @ 10 mhz pfd frequency ?152 dbc/hz @ 50 mhz pfd frequency ?144 dbc/hz pll figure of merit (fom) ?222 dbc/hz reference slew rate > 0.5 v/ns; fom + 10 log(f pfd ) is an approximation of the pfd/cp in-band phase noise (in the flat region) inside the pll loop bandwidth; when running closed-loop, the phase noise, as observed at the vco output, is increased by 20 log(n); pll figure of merit decreases with decreasing slew rate; see figure 11 pll digital lock detect window 2 signal available at the ld, status, and refmon pins when selected by appropriate register settings; lock detect window settings can be varied by changing the cprset resistor lock threshold (coincidence of edges) selected by 0x017[1:0] and 0x0 18[4] (this is the threshold to go from unlock to lock) low range (abp 1.3 ns, 2.9 ns) 3.5 ns 0x017[1:0] = 00b, 01b,11b; 0x018[4] = 1b high range (abp 1.3 ns, 2.9 ns) 7.5 ns 0x017[1:0] = 00b, 01b, 11b; 0x018[4] = 0b high range (abp 6.0 ns) 3.5 ns 0x017[1:0] = 10b; 0x018[4] = 0b unlock threshold (hysteresis) 2 selected by 0x017[1:0] and 0x0 18[4] (this is the threshold to go from lock to unlock) low range (abp 1.3 ns, 2.9 ns) 7 ns 0x017[1:0] = 00b, 01b, 11b; 0x018[4] = 1b high range (abp 1.3 ns, 2.9 ns) 15 ns 0x017[1:0] = 00b, 01b, 11b; 0x018[4] = 0b high range (abp 6.0 ns) 11 ns 0x017[1:0] = 10b; 0x018[4] = 0b 1 the refin and refin self-bias points are offset slightly to avoid chatter on an open input condition. 2 for reliable operation of the digital lock detect, the period of the pfd frequency must be greater than the unlock-after-lock time.
ad9520-5 rev. 0 | page 7 of 80 clock inputs table 3. parameter min typ max unit test conditions/comments clock inputs (clk, clk ) differential input input frequency 0 1 2.4 ghz high frequency distribution (vco divider) 0 1 1.6 ghz distribution only (vco divider bypassed); this is the frequency range supported by the channel divider input sensitivity, differential 150 mv p-p measured at 2.4 ghz; jitter performance is improved with slew rates > 1 v/ns input level, differential 2 v p-p larger voltage swings can turn on the protection diodes and can degrade jitter performance input common-mode voltage, v cm 1.3 1.57 1.8 v self-biased; enables ac coupling input common-mode range, v cmr 1.3 1.8 v with 200 mv p-p signal applied; dc-coupled input sensitivity, single-ended 150 mv p-p clk ac-coupled; clk ac-bypassed to rf ground input resistance 3.9 4.7 5.7 k self-biased input capacitance 2 pf 1 below about 1 mhz, the input should be dc-coupled. care should be taken to match v cm . clock outputs table 4. parameter min typ max unit test conditions/comments lvpecl clock outputs termination = 50 to vs_drv ? 2 v out0, out1, out2, out3, out4, out5, out6, out7, out8, out9, out10, out11 differential (out, out ) output frequency, maximum 2400 mhz using direct to output; see figure 17 (higher frequencies are possible, but amplitude will not meet the v od specification); the maximum output frequency is limited by the maximum frequency at the clk inputs output high voltage, v oh vs_drv ? 1.07 vs_drv ? 0.96 vs_drv ? 0.84 v output low voltage, v ol vs_drv ? 1.95 vs_drv ? 1.79 vs_drv ? 1.64 v output differential voltage, v od 660 820 950 mv cmos clock outputs out0a, out0b, out1a, out1b, out2a, out2b, out3a, out3b, out4a, out4b, out5a, out5b, out6a, out6b, out7a, out7b, out8a, out8b, out9a, out9b, out10a, out10b, out11a, out11b single-ended; termination = 10 pf output frequency 250 mhz see figure 18 output voltage high, v oh vs ? 0.1 v @ 1 ma load, vs_drv = 3.3 v/2.5 v output voltage low, v ol 0.1 v @ 1 ma load, vs_drv = 3.3 v/2.5 v output voltage high, v oh 2.7 v @ 10 ma load, vs_drv = 3.3 v output voltage low, v ol 0.5 v @ 10 ma load, vs_drv = 3.3 v output voltage high, v oh 1.8 v @ 10 ma load, vs_drv = 2.5 v output voltage low, v ol 0.6 v @ 10 ma load, vs_drv = 2.5 v
ad9520-5 rev. 0 | page 8 of 80 timing characteristics table 5. parameter min typ max unit test conditions/comments lvpecl output rise/fall times termination = 50 to vs_drv ? 2 v output rise time, t rp 130 170 ps 20% to 80%, measured differentially (rise/fall times are independent of vs and are valid for vs_drv = 3.3 v and 2.5 v) output fall time, t fp 130 170 ps 80% to 20%, measured differentially (rise/fall times are independent of vs and are valid for vs_drv = 3.3 v and 2.5 v) propagation delay, t pecl , clk-to-lvpecl output for all divide values 850 1050 1280 ps high frequency clock distribution configuration 800 970 1180 ps clock distribution configuration variation with temperature 1.0 ps/c output skew, lvpecl outputs 1 termination = 50 to vs_drv ? 2 v lvpecl outputs that share the same divider 5 16 ps vs_drv = 3.3 v 5 20 ps vs_drv = 2.5 v lvpecl outputs on different dividers 5 45 ps vs_drv = 3.3 v 5 60 ps vs_drv = 2.5 v all lvpecl outputs across multiple parts 190 ps vs_drv = 3.3 v and 2.5 v cmos output rise/fall times termination = open output rise time, t rc 750 960 ps 20% to 80%; c load = 10 pf; vs_drv = 3.3 v output fall time, t fc 715 890 ps 80% to 20%; c load = 10 pf; vs_drv = 3.3 v output rise time, t rc 965 1280 ps 20% to 80%; c load = 10 pf; vs_drv = 2.5 v output fall time, t fc 890 1100 ps 80% to 20%; c load = 10 pf; vs_drv = 2.5 v propagation delay, t cmos , clk-to-cmos output clock distribution configuration for all divide values 2.1 2.75 3.55 ns vs_drv = 3.3 v 3.35 ns vs_drv = 2.5 v variation with temperature 2 ps/c vs_drv = 3.3 v and 2.5 v output skew, cmos outputs 1 cmos outputs that share the same divider 7 85 ps vs_drv = 3.3 v 10 105 ps vs_drv = 2.5 v all cmos outputs on different dividers 10 240 ps vs_drv = 3.3 v 10 285 ps vs_drv = 2.5 v all cmos outputs across multiple parts 600 ps vs_drv = 3.3 v 620 ps vs_drv = 2.5 v output skew, lvpecl-to-cmos output 1 all settings identical; different logic type outputs that share the same divider 1.18 1.76 2.48 ns lvpecl to cmos on same part outputs that are on different dividers 1.20 1.78 2.50 ns lvpecl to cmos on same part 1 the output skew is the difference betw een any two similar delay paths while operat ing at the same voltage and temperature.
ad9520-5 rev. 0 | page 9 of 80 timing diagrams cl k t cmos t clk t pecl 07239-060 figure 2. clk/ clk to clock output timing, div = 1 differential lvpecl 80% 20% t rp t fp 07239-061 figure 3. lvpecl timing, differential single-ended cmos 10pf load 80% 20% t rc t fc 07239-063 figure 4. cmos timing, si ngle-ended, 10 pf load
ad9520-5 rev. 0 | page 10 of 80 clock output additive phase noise (distribution only; vco divider not used) table 6. parameter min typ max unit test conditions/comments clk-to-lvpecl additive phase noise distri bution section only; does not include the pll clk = 1 ghz, output = 1 ghz input slew rate > 1 v/ns divider = 1 @ 10 hz offset ?107 dbc/hz @ 100 hz offset ?117 dbc/hz @ 1 khz offset ?127 dbc/hz @ 10 khz offset ?135 dbc/hz @ 100 khz offset ?142 dbc/hz @ 1 mhz offset ?145 dbc/hz @ 10 mhz offset ?147 dbc/hz @ 100 mhz offset ?150 dbc/hz clk = 1 ghz, output = 200 mhz input slew rate > 1 v/ns divider = 5 @ 10 hz offset ?122 dbc/hz @ 100 hz offset ?132 dbc/hz @ 1 khz offset ?143 dbc/hz @ 10 khz offset ?150 dbc/hz @ 100 khz offset ?156 dbc/hz @ 1 mhz offset ?157 dbc/hz >10 mhz offset ?157 dbc/hz clk-to-cmos additive phase noise distrib ution section only; does not include the pll clk = 1 ghz, output = 250 mhz input slew rate > 1 v/ns divider = 4 @ 10 hz offset ?107 dbc/hz @ 100 hz offset ?119 dbc/hz @ 1 khz offset ?125 dbc/hz @ 10 khz offset ?134 dbc/hz @ 100 khz offset ?144 dbc/hz @ 1 mhz offset ?148 dbc/hz >10 mhz offset ?154 dbc/hz clk = 1 ghz, output = 50 mhz input slew rate > 1 v/ns divider = 20 @ 10 hz offset ?126 dbc/hz @ 100 hz offset ?133 dbc/hz @ 1 khz offset ?140 dbc/hz @ 10 khz offset ?148 dbc/hz @ 100 khz offset ?157 dbc/hz @ 1 mhz offset ?160 dbc/hz >10 mhz offset ?163 dbc/hz
ad9520-5 rev. 0 | page 11 of 80 clock output absolute time jitter (clock generation using external vcxo) table 7. parameter min typ max unit test conditions/comments lvpecl output absolute time jitter application example based on a typical setup using an external 245.76 mhz vcxo (toyocom tco-2112); reference = 15.36 mhz; r div = 1 lvpecl = 245.76 mhz; pll lbw = 125 hz 54 fs rms integration bw = 200 khz to 5 mhz 77 fs rms integration bw = 200 khz to 10 mhz 109 fs rms integration bw = 12 khz to 20 mhz lvpecl = 122.88 mhz; pll lbw = 125 hz 79 fs rms integration bw = 200 khz to 5 mhz 114 fs rms integration bw = 200 khz to 10 mhz 163 fs rms integration bw = 12 khz to 20 mhz lvpecl = 61.44 mhz; pll lbw = 125 hz 124 fs rms integration bw = 200 khz to 5 mhz 176 fs rms integration bw = 200 khz to 10 mhz 259 fs rms integration bw = 12 khz to 20 mhz clock output additive time jitter (vco divider not used) table 8. parameter min typ max unit test conditions/comments lvpecl output additive time jitter distribution section only; does not include the pll; measured at rising edge of clock signal clk = 622.08 mhz 46 fs rms integration bandwidth = 12 khz to 20 mhz any lvpecl output = 622.08 mhz divide ratio = 1 clk = 622.08 mhz 64 fs rms integration bandwidth = 12 khz to 20 mhz any lvpecl output = 155.52 mhz divide ratio = 4 clk = 1000 mhz 223 fs rms calculated from snr of adc method any lvpecl output = 100 mhz broadband jitter divide ratio = 10 clk = 500 mhz 209 fs rms calculated from snr of adc method any lvpecl output = 100 mhz broadband jitter divide ratio = 5 cmos output additive time jitter dist ribution section only; does not include the pll clk = 200 mhz 325 fs rms calculated from snr of adc method any cmos output pair = 100 mhz broadband jitter divide ratio = 2
ad9520-5 rev. 0 | page 12 of 80 clock output additive time jitter (vco divider used) table 9. parameter min typ max unit test conditions/comments lvpecl output additive time jitter distribution section only; does not include pll and vco; uses rising edge of clock signal clk = 1.0 ghz; vco div = 5; lvpecl = 100 mhz; channel divider = 2; duty-cycle correction = off 230 fs rms calculated from snr of adc method (broadband jitter) clk = 500 mhz; vco div = 5; lvpecl = 100 mhz; bypass channel divider; duty-cycle correction = on 215 fs rms calculated from snr of adc method (broadband jitter) cmos output additive time jitter distribution section only; does not include pll; uses rising edge of clock signal clk = 200 mhz; vco div = 2; cmos = 100 mhz; bypass channel divider; duty-cycle correction = off 326 fs rms calculated from snr of adc method (broadband jitter) clk = 1600 mhz; vco div = 2; cmos = 100 mhz; channel divider = 8; duty-cycle correction = off 362 fs rms calculated from snr of adc method (broadband jitter) serial control portspi mode table 10. parameter min typ max unit test conditions/comments cs (input) cs has an internal 30 k pull-up resistor input logic 1 voltage 2.0 v input logic 0 voltage 0.8 v input logic 1 current 3 a input logic 0 current ?110 a the minus sign indicates that current is flowing out of the ad9520, which is due to the internal pull-up resistor input capacitance 2 pf sclk (input) in spi mode sclk has an internal 30 k pull-down resistor in spi mode, but not in i 2 c mode input logic 1 voltage 2.0 v input logic 0 voltage 0.8 v input logic 1 current 110 a input logic 0 current 1 a input capacitance 2 pf sdio (when an input in bidirectional mode) input logic 1 voltage 2.0 v input logic 0 voltage 0.8 v input logic 1 current 1 a input logic 0 current 1 a input capacitance 2 pf sdio, sdo (outputs) output logic 1 voltage 2.7 v output logic 0 voltage 0.4 v timing clock rate (sclk, 1/t sclk ) 25 mhz pulse width high, t high 16 ns pulse width low, t low 16 ns sdio to sclk setup, t ds 4 ns sclk to sdio hold, t dh 0 ns sclk to valid sdio and sdo, t dv 11 ns cs to sclk setup and hold, t s , t c 2 ns cs minimum pulse width high, t pwh 3 ns
ad9520-5 rev. 0 | page 13 of 80 serial control porti2c mode table 11. parameter min typ max unit test conditions/comments sda, scl (when inputting data) input logic 1 voltage 0.7 vs v input logic 0 voltage 0.3 vs v input current with an input voltage between 0.1 vs and 0.9 vs ?10 +10 a hysteresis of schmitt trigger inputs 0.015 vs v pulse width of spikes that must be suppressed by the input filter, t spike 50 ns sda (when outputting data) output logic 0 voltage at 3 ma sink current 0.4 v output fall time from vih min to vil max with a bus capacitance from 10 pf to 400 pf 20 + 0.1 c b 250 ns c b = capacitance of one bus line in pf timing note that all i 2 c timing values referred to vih min (0.3 vs) and vil max levels (0.7 vs) clock rate (scl, f i2c ) 400 khz bus free time between a stop and start condition, t idle 1.3 s setup time for a repeated start condition, t set; str 0.6 s hold time (repeated) start condition (after this period, the first clock pulse is generated), t hld; str 0.6 s setup time for stop condition, t set; stp 0.6 s low period of the scl clock, t low 1.3 s high period of the scl clock, t high 0.6 s scl, sda rise time, t rise 20 + 0.1 c b 300 ns scl, sda fall time, t fall 20 + 0.1 c b 300 ns data setup time, t set; dat 120 ns this is a minor deviation from the original i2c specification of 100 ns minimum data hold time, t hld; dat 140 880 ns this is a minor deviation from the original i2c specification of 0 ns minimum 1 capacitive load for each bus line, c b 400 pf 1 according to the original i 2 c specification, an i 2 c master must also provide a minimum hold time of 300 ns for the sda signal to bridge the undefined region of the scl falling edge.
ad9520-5 rev. 0 | page 14 of 80 pd , sync , and reset pins table 12. parameter min typ max unit test conditions/comments input characteristics each of these pins has a 30 k internal pull-up resistor logic 1 voltage 2.0 v logic 0 voltage 0.8 v logic 1 current 1 a logic 0 current ?110 a the minus sign indicates that current is flowing out of the ad9520, which is due to the internal pull-up resistor capacitance 2 pf reset timing pulse width low 50 ns reset inactive to start of register programming 100 ns sync timing pulse width low 1.3 ns high speed clock is clk input signal serial port setup pins: sp1, sp0 table 13. parameter min typ max unit test conditions/comments sp1, sp0 these pins do not have internal pull-up/pull-down resistors logic level 0 0.25 vs v vs is the voltage on the vs pin logic level ? 0.4 vs 0.65 vs v user can float these pins to obtain logic level ?; if floating this pin, user should connect a capacitor to ground logic level 1 0.8 vs v ld, status, and refmon pins table 14. parameter min typ max unit test conditions/comments output characteristics when selected as a digital output (cmos); there are other modes in which these pins ar e not cmos digital outputs; see table 48 , 0x017, 0x01a, and 0x01b output voltage high, v oh 2.7 v output voltage low, v ol 0.4 v maximum toggle rate 100 mhz applies when mux is set to any divider or counter output or pfd up/down pulse; also applies in analog lock detect mode; usually debug mode on ly; beware that spurs can couple to output when any of these pins is toggling analog lock detect capacitance 3 pf on-chip capacitance; used to calculate rc time constant for analog lock detect readback; use a pull-up resistor ref1, ref2, and clk frequency status monitor normal range 1.02 mhz frequency above which the monitor indicates the presence of the reference extended range 8 khz frequency above which the monitor indicates the presence of the reference ld pin comparator trip point 1.6 v hysteresis 260 mv
ad9520-5 rev. 0 | page 15 of 80 power dissipation table 15. parameter min typ max unit test conditions/comments power dissipation, chip does not include power dissipated in external resistors; all lvpecl outputs terminated with 50 to v cc ? 2 v; all cmos outputs have 10 pf capacitive loading; vs_drv = 3.3 v power-on default 1.32 1.5 w no clock; no programming; default register values distribution only mode; vco divider on; one lvpecl output enabled 0.39 0.46 w f clk = 2.4 ghz; f out = 200 mhz; vco divider = 2; one lvpecl output and output divider en abled; zero delay off distribution only mode; vco divider off; one lvpecl output enabled 0.36 0.42 w f clk = 2.4 ghz; f out = 200 mhz; vco divider bypassed; one lvpecl output and output divider enabled; zero delay off maximum power, full operation 1.4 1.7 w pll on; vco divider = 2; all channel dividers on; 12 lvpecl outputs @ 125 mhz; zero delay on pd power-down 60 80 mw pd pin pulled low; does not include power dissipated in termination resistors pd power-down, maximum sleep 24 33 mw pd pin pulled low; pll power-down, 0x010[1:0] = 01b; power-down sync, 0x230[2] = 1b; power-down distribution reference, 0x230[1] = 1b vcp supply 4 4.8 mw pll operating; typical closed-lo op configuration power deltas, individual functions power delta when a function is enabled/disabled vco divider on/off 32 40 mw vco divider not used refin (differential) off 25 30 mw delta between reference input off and differential reference input mode ref1, ref2 (single-ended) on/off 15 20 mw delta between reference inputs off and one singled-ended reference enabled; double this number if both ref1 and ref2 are powered up pll dividers and phase detector on/off 51 63 mw pll off to pll on, normal operation; no reference enabled lvpecl channel 121 144 mw no lvpecl output on to one lvpe cl output on; channel divider set to 1 lvpecl driver 51 73 mw second lvpecl output turned on, same channel cmos channel 145 180 mw no cmos output on to one cmos output on; channel divider set to 1; f out = 62.5 mhz and 10 pf of capacitive loading cmos driver on/off 11 24 mw additional cmos outputs within the sa me channel turned on channel divider enabled 40 57 mw delta between divider bypassed (divide-by-1) and divide-by-2 to divide-by-32 zero delay block on/off 30 34 mw
ad9520-5 rev. 0 | page 16 of 80 absolute maximum ratings table 16. parameter or pin with respect to rating vs gnd ?0.3 v to +3.6 v vcp, cp gnd ?0.3 v to +5.8 v vs_drv gnd ?0.3 v to +3.6 v refin, refin gnd ?0.3 v to vs + 0.3 v rset gnd ?0.3 v to vs + 0.3 v cprset gnd ?0.3 v to vs + 0.3 v clk, clk gnd ?0.3 v to vs + 0.3 v clk clk ?1.2 v to +1.2 v sclk/scl, sdio/sda, sdo, cs gnd ?0.3 v to vs + 0.3 v out0, out0 , out1, out1 , out2, out2 , out3, out3 , out4, out4 , out5, out5 , out6, out6 , out7, out7 , out8, out8 , out9, out9 , out10, out10 , out11, out11 gnd ?0.3 v to vs + 0.3 v sync , reset , pd gnd ?0.3 v to vs + 0.3 v refmon, status, ld gnd ?0.3 v to vs + 0.3 v sp0, sp1, eeprom gnd ?0.3 v to vs + 0.3 v junction temperature 1 150c storage temperature range ?65c to +150c lead temperature (10 sec) 300c 1 see table 17 for ja . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance thermal impedance measurements were taken on a jedec jesd51-5 2s2p test board in still air in accordance with jedec jesd51-2. see the thermal performance section for more details. table 17. package type ja unit 64-lead lfcsp (cp-64-4) 22 c/w esd caution
ad9520-5 rev. 0 | page 17 of 80 notes 1. exposed die pad must be connected to gnd. pin configuration and fu nction descriptions pin 1 indicator 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 sdio/sda sdo gnd sp1 sp0 eeprom reset pd t9 (out9a) t9 (out9b) vs_drv out10a) out10b) out11a) out11b) vs 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 refin (ref1) refin (ref2) cprset vs vs gnd rset vs out0 (out0a) out0 (out0b) vs_drv out1 (out1a) out1 (out1b) out2 (out2a) out2 (out2b) vs 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vs refmon ld vcp cp status ref_sel sync nc nc vs vs clk clk cs sclk/scl out3 (out3a) out3 (out3b) vs_drv out4 (out4a) out4 (out4b) out5 (out5a) out5 (out5b) vs vs out8 (out8b) out8 (out8a) out7 (out7b) out7 (out7a) vs_drv out6 (out6b) out6 (out6a) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ou ou out10 ( out10 ( out11 ( out11 ( ad9520-5 top view (not to scale) 07239-003 figure 5. pin configuration table 18. pin function descriptions pin no. input/ output pin type mnemonic description 1, 11, 12, 32, 40, 41,49, 57, 60, 61 i power vs 3.3 v power pins. 2 o 3.3 v cmos refmon reference monitor (output) . this pin has multiple selectable outputs. 3 o 3.3 v cmos ld lock detect (output). this pin has multiple selectable outputs. 4 i power vcp power supply for charge pump (cp); vs < vcp < 5.0 v. vcp must still be connected to 3.3 v if the pll is not used. 5 o loop filter cp charge pump (output). this pin connects to an external loop filter. this pin can be left unconnected if the pll is not used. 6 o 3.3 v cmos status programmable status output. 7 i 3.3 v cmos ref_sel reference select. it selects ref1 (low) or ref2 (high). this pin has an internal 30 k pull-down resistor. 8 i 3.3 v cmos sync manual synchronization and manual ho ldover. this pin initiates a manual synchronization and is used for manual holdover. active low. this pin has an internal 30 k pull-up resistor. 9, 10 nc no connect. these pins can be left floating. along with clk , this pin is the differential input for the clock distribution section. 13 i differential clock input clk 14 i differential clock input clk along with clk, this pin is the differential input for the clock distribution section. if a single-ended input is connected to the clk pin, connect a 0.1 f bypass capacitor from clk to ground.
ad9520-5 rev. 0 | page 18 of 80 pin no. input/ output pin type mnemonic description 15 i 3.3 v cmos cs serial control port chip select; active low. this pin has an internal 30 k pull-up resistor. 16 i 3.3 v cmos sclk/scl serial control port clock signal. this pin has an internal 30 k pull-down resistor in spi mode but is high impedance in i2c mode. 17 i/o 3.3 v cmos sdio/sda serial control port bidirectional serial data in/out. 18 o 3.3 v cmos sdo serial control port unidirectional serial data out. 19, 59 i gnd gnd ground pins. 20 i three-level logic sp1 select spi or i2c as the serial interface port and select the i2c slave address in i2c mode. three-level logic. this pin is internally biased for the open logic level. 21 i three-level logic sp0 select spi or i2c as the serial interface port and select the i2c slave address in i2c mode. three-level logic. this pin is internally biased for the open logic level. 22 i 3.3 v cmos eeprom setting this pin high selects the register values stored in the internal eeprom to be loaded at reset and/or power-up. se tting this pin low causes the ad9520 to load the hard-coded default register values at power-up/reset. this pin has an internal 30 k pull-down resistor. 23 i 3.3 v cmos reset chip reset, active low. this pin has an internal 30 k pull-up resistor. 24 i 3.3 v cmos pd chip power-down, active low. this pin has an internal 30 k pull-up resistor. 25 o lvpecl or cmos out9 (out9a) clock output. this pin can be configured as one side of a differential lvpecl output or as a single-ended cmos output. 26 o lvpecl or cmos out9 (out9b) clock output. this pin can be config ured as one side of a differential lvpecl output or as a single-ended cmos output. 27, 35, 46, 54 i power vs_drv output driver power supply pins. as a grou p, these pins can be set to either 2.5 v or 3.3 v. all four pins must be set to the same voltage. 28 o lvpecl or cmos out10 (out10a) clock output. this pin can be configured as one side of a differential lvpecl output or as a single-ended cmos output. 29 o lvpecl or cmos out10 (out10b) clock output. this pin can be configured as one side of a differential lvpecl output or as a single-ended cmos output. 30 o lvpecl or cmos out11 (out11a) clock output. this pin can be configured as one side of a differential lvpecl output or as a single-ended cmos output. 31 o lvpecl or cmos out11 (out11b) clock output. this pin can be config ured as one side of a differential lvpecl output or as a single-ended cmos output. 33 o lvpecl or cmos out6 (out6a) clock output. this pin can be configured as one side of a differential lvpecl output or as a single-ended cmos output. 34 o lvpecl or cmos out6 (out6b) clock output. this pin can be config ured as one side of a differential lvpecl output or as a single-ended cmos output. 36 o lvpecl or cmos out7 (out7a) clock output. this pin can be configured as one side of a differential lvpecl output or as a single-ended cmos output. 37 o lvpecl or cmos out7 (out7b) clock output. this pin can be config ured as one side of a differential lvpecl output or as a single-ended cmos output. 38 o lvpecl or cmos out8 (out8a) clock output. this pin can be configured as one side of a differential lvpecl output or as a single-ended cmos output. 39 o lvpecl or cmos out8 (out8b) clock output. this pin can be configured as one side of a differential lvpecl output or as a single-ended cmos output. 42 o lvpecl or cmos out5 (out5b) clock output. this pin can be config ured as one side of a differential lvpecl output or as a single-ended cmos output. 43 o lvpecl or cmos out5 (out5a) clock output. this pin can be configured as one side of a differential lvpecl output or as a single-ended cmos output. 44 o lvpecl or cmos out4 (out4b) clock output. this pin can be config ured as one side of a differential lvpecl output or as a single-ended cmos output. 45 o lvpecl or cmos out4 (out4a) clock output. this pin can be configured as one side of a differential lvpecl output or as a single-ended cmos output.
ad9520-5 rev. 0 | page 19 of 80 pin no. input/ output pin type mnemonic description 47 o lvpecl or cmos out3 (out3b) clock output. this pin can be config ured as one side of a differential lvpecl output or as a single-ended cmos output. 48 o lvpecl or cmos out3 (out3a) clock output. this pin can be configured as one side of a differential lvpecl output or as a single-ended cmos output. 50 o lvpecl or cmos out2 (out2b) clock output. this pin can be config ured as one side of a differential lvpecl output or as a single-ended cmos output. 51 o lvpecl or cmos out2 (out2a) clock output. this pin can be configured as one side of a differential lvpecl output or as a single-ended cmos output. 52 o lvpecl or cmos out1 (out1b) clock output. this pin can be config ured as one side of a differential lvpecl output or as a single-ended cmos output. 53 o lvpecl or cmos out1 (out1a) clock output. this pin can be configured as one side of a differential lvpecl output or as a single-ended cmos output. 55 o lvpecl or cmos out0 (out0b) clock output. this pin can be config ured as one side of a differential lvpecl output or as a single-ended cmos output. 56 o lvpecl or cmos out0 (out0a) clock output. this pin can be configured as one side of a differential lvpecl output or as a single-ended cmos output. 58 o current set resistor rset clock distribution current set resistor. connect a 4.12 k resistor from this pin to gnd. 62 o current set resistor cprset charge pump current set resistor. connect a 5.1 k resistor from this pin to gnd. this resistor can be omitted if the pll is not used. 63 i reference input refin (ref2) along with refin, this is the differen tial input for the pll reference. alternatively, this pin is a single-ended input for ref2. this pin can be left unconnected when the pll is not used. 64 i reference input refin (ref1) along with refin , this is the differential input fo r the pll reference. alternatively, this pin is a single-ended input for ref1.this pin can be left unconnected when the pll is not used. epad gnd gnd the exposed die pa d must be connected to gnd.
ad9520-5 rev. 0 | page 20 of 80 typical performance characteristics 350 300 250 200 150 100 0 500 1000 1500 2000 2500 3000 current (ma) frequency (mhz) 3 channels?6 lvpecl 3 channels?3 lvpecl 2 channels?2 lvpecl 1 channel?1 lvpecl 07239-108 figure 6. total current vs. frequency, clk-to-output (pll off), lvpecl outputs terminated 50 to vs_drv ? 2 v 240 220 200 180 160 140 120 100 80 0 50 100 150 200 250 current (ma) frequency (mhz) 3 channels?6 cmos 3 channels?3 cmos 2 channels?2 cmos 1 channel?1 cmos 07239-109 figure 7. total current vs. frequency, clk-to-output (pll off), cmos outputs with 10 pf load 5 4 3 2 1 0 03 3.0 2.5 2.0 1.5 1.0 0.5 current from cp pin (ma) voltage on cp pin (v) . 5 pump up pump down 07239-111 figure 8. charge pump characteristics @ vcp = 3.3 v 5 4 3 2 1 0 05 4.0 3.0 4.5 3.5 2.52.01.51.00.5 current from cp pin (ma) voltage on cp pin (v) . 0 pump down pump up 07239-112 figure 9. charge pump characteristics @ vcp = 5.0 v ? 140 ?145 ?150 ?155 ?160 ?165 ?170 0.1 1 100 10 pfd phase noise referred to pfd input (dbc/hz) pfd frequency (mhz) 07239-013 figure 10. pfd phase noise referred to pfd input vs. pfd frequency ? 208 ?210 ?212 ?214 ?216 ?218 ?220 ?222 ?224 0 0.4 0.8 1.2 0.2 0.6 1.0 1.4 pll figure of merit (dbc/hz) input slew rate (v/ns) differential input single-ended input 07239-114 figure 11. pll figure of merit (fom) vs. slew rate at refin/ refin
ad9520-5 rev. 0 | page 21 of 80 3.5 0 0.5 1.0 1.5 2.0 2.5 3.0 v oh (v) 10k 1k 100 resistive load ( ? ) vs_drv = 3.135v vs_drv = 2.35v vs_drv = 3.3v vs_drv = 2.5v 07239-118 figure 12. cmos output v oh (static) vs. r load (to ground) 1.2 0.8 0.4 0 ?0.4 ?0.8 ?1.2 02 222018 1614 1210 8642 differential output (v) time (ns) 4 07239-014 figure 13. lvpecl output (differential) @ 100 mhz 1.0 0.6 0.2 ?0.2 ?0.6 ?1.0 01 0.5 1.0 differential swing (v p-p) time (ns) . 5 07239-015 figure 14. lvpecl differential voltage swing @ 1600 mhz 3.2 2.8 2.4 2.0 1.6 1.2 0.8 0.4 0 08 60 100 40 20 70 50 90 30 10 amplitude (v) time (ns) 0 07239-018 figure 15. cmos output with 10 pf load @ 25 mhz 3.2 2.8 2.4 2.0 1.6 1.2 0.8 0.4 0 01 987654321 amplitude (v) time (ns) 0 2pf load 10pf load 07239-019 figure 16. cmos output with 2 pf and 10 pf load @ 250 mhz 2.0 1.8 1.6 1.4 1.2 1.0 03 1.5 2.0 2.5 1.0 0.5 differential swing (v p-p) frequency (ghz) . 0 07239-123 figure 17. lvpecl differential voltage swing vs. frequency
ad9520-5 rev. 0 | page 22 of 80 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 07 2pf 10pf 20pf 600 500 400 300 200 100 amplitude (v) frequency (mhz) 0 0 07239-124 figure 18. cmos output swing vs. frequency and capacitive load ? 100 ?110 ?120 ?130 ?140 ?150 ?160 10 1k 100 100m 1m 10m 100k 10k phase noise (dbc/hz) frequency (hz) 07239-128 figure 19. additive (residual) phase noise, clk-to-lvpecl @ 245.76 mhz, divide-by-1 ? 100 ?110 ?120 ?130 ?140 ?150 ?160 10 1k 100 100m 1m 10m 100k 10k phase noise (dbc/hz) frequency (hz) 07239-130 figure 20. additive (residual) phase noise, clk-to-lvpecl @ 1600 mhz, divide-by-1 ? 110 ?120 ?130 ?140 ?150 ?170 ?160 10 1k 100 100m 1m 10m 100k 10k phase noise (dbc/hz) frequency (hz) 07239-131 figure 21. additive (residual) phase noise, clk-to-cmos @ 50 mhz, divide-by-20
ad9520-5 rev. 0 | page 23 of 80 ? 100 ?110 ?120 ?130 ?140 ?150 ?160 10 1k 100 100m 1m 10m 100k 10k phase noise (dbc/hz) frequency (hz) 07239-129 figure 22. additive (residual) phase noise, clk-to-lvpecl @ 200 mhz, divide-by-5 ? 100 ?110 ?120 ?130 ?140 ?150 ?160 10 1k 100 100m 1m 10m 100k 10k phase noise (dbc/hz) frequency (hz) 07239-132 figure 23. additive (residual) phase noise, clk-to-cmos @ 250 mhz, divide-by-4 1k 100m 1m 10m 100k 10k phase noise (dbc/hz) frequency (hz) ? 120 ?160 ?150 ?140 ?130 07239-135 figure 24. phase noise (absolute), external vcxo (toyocom tco-2112) @ 245.76 mhz; pfd = 15.36 mhz; lbw = 250 hz; lvpecl output = 245.76 mhz
ad9520-5 rev. 0 | page 24 of 80 terminology phase jitter and phase noise an ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0 to 360 for each cycle. actual signals, however, display a certain amount of variation from ideal phase progression over time. this phenomenon is called phase jitter. although many causes can contribute to phase jitter, one major cause is random noise, which is characterized statistically as being gaussian (normal) in distribution. this phase jitter leads to a spreading out of the energy of the sine wave in the frequency domain, producing a continuous power spectrum. this power spectrum is usually reported as a series of values whose units are dbc/hz at a given offset in frequency from the sine wave (carrier). the value is a ratio (expressed in decibels) of the power contained within a 1 hz bandwidth with respect to the power at the carrier frequency. for each measurement, the offset from the carrier frequency is also given. it is meaningful to integrate the total power contained within some interval of offset frequencies (for example, 10 khz to 10 mhz). this is called the integrated phase noise over that frequency offset interval and can be readily related to the time jitter due to the phase noise within that offset frequency interval. phase noise has a detrimental effect on the performance of adcs, dacs, and rf mixers. it lowers the achievable dynamic range of the converters and mixers, although they are affected in somewhat different ways. time jitter phase noise is a frequency domain phenomenon. in the time domain, the same effect is exhibited as time jitter. when observing a sine wave, the time of successive zero crossings varies. in a square wave, the time jitter is a displacement of the edges from their ideal (regular) times of occurrence. in both cases, the variations in timing from the ideal are the time jitter. because these variations are random in nature, the time jitter is specified in seconds root mean square (rms) or 1 sigma of the gaussian distribution. time jitter that occurs on a sampling clock for a dac or an adc decreases the signal-to-noise ratio (snr) and dynamic range of the converter. a sampling clock with the lowest possible jitter provides the highest performance from a given converter. additive phase noise additive phase noise is the amount of phase noise that is attributable to the device or subsystem being measured. the phase noise of any external oscillators or clock sources is subtracted. this makes it possible to predict the degree to which the device impacts the total system phase noise when used in conjunction with the various oscillators and clock sources, each of which contributes its own phase noise to the total. in many cases, the phase noise of one element dominates the system phase noise. when there are multiple contributors to phase noise, the total is the square root of the sum of squares of the individual contributors. additive time jitter additive time jitter is the amount of time jitter that is attributable to the device or subsystem being measured. the time jitter of any external oscillators or clock sources is subtracted. this makes it possible to predict the degree to which the device impacts the total system time jitter when used in conjunction with the various oscillators and clock sources, each of which contributes its own time jitter to the total. in many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter.
ad9520-5 rev. 0 | page 25 of 80 detailed block diagram programmable n delay refin clk clk ref1 ref2 buf amp ad9520-5 status status r divider clock doubler status programmable r delay reference switchover ref_sel cprset v cp v s gnd rset distribution reference refmon cp vs_drv status ld p, p + 1 prescaler a/b counters n divider phase frequency detector lock detect charge pump pll reference hold 01 divide by 1, 2, 3, 4, 5, or 6 pd sync refin reset eeprom digital logic eeprom divide by 1 to 32 out0 out0 out1 out1 out2 out2 divide by 1 to 32 out3 out3 out4 out4 out5 out5 divide by 1 to 32 out6 out6 out7 out7 out8 out8 divide by 1 to 32 out9 out9 out10 out10 out11 out11 zero delay block lvpecl/cmos output sp1 sp0 spi interface i 2 c interface sclk/scl sdio/sda sdo cs serial port decode optional 07239-028 figure 25.
ad9520-5 rev. 0 | page 26 of 80 theory of operation operational configurations the ad9520 can be configured in several ways. these configurations must be set up by loading the control registers (see table 44 to table 55 ). each section or function must be individually programmed by setting the appropriate bits in the corresponding control register or registers. when the desired configuration is programmed, the user can store these values in the on-board eeprom to allow the part to power up in the desired configuration without user intervention. mode 1: clock distribution or external vco < 1600 mhz when the external clock source to be distributed or the external vco/vcxo is <1600 mhz, a configuration that bypasses the vco divider can be used. this is the only difference from mode 2. bypassing the vco divider limits the frequency of the clock source to <1600 mhz (due to the maximum input frequency allowed at the channel dividers). configuration and register settings for clock distribution applications where the external clock is <1600 mhz, the register settings shown in table 19 should be used. table 19. settings for clock distribution < 1600 mhz register description 0x010[1:0] = 01b pll asynchronous power-down (pll off ) 0x1e1[0] = 1b bypass the vco divider as the source for the distribution section 0x1e1[1] = 0b clk selected as the source when using the internal pll with an external vco < 1600 mhz, the pll must be turned on. table 20. settings for using internal pll with external vco < 1600 mhz register description 0x1e1[0] = 1b bypass the vco divider as the source for the distribution section 0x010[1:0] = 00b pll normal operation (pll on) along with other appropriate pll settings in 0x010 to 0x01e an external vco/vcxo requires an external loop filter that must be connected between cp and the tuning pin of the vco/ vcxo. this loop filter determines the loop bandwidth and stability of the pll. make sure to select the proper pfd polarity for the vco/vcxo being used. table 21. setting the pfd polarity register description 0x010[7] = 0b pfd polarity positive (higher control voltage produces higher frequency) 0x010[7] = 1b pfd polarity negative (higher control voltage produces lower frequency)
ad9520-5 rev. 0 | page 27 of 80 programmable n delay refin clk clk ref1 ref2 buf amp ad9520-5 r divider clock doubler status programmable r delay reference switchover ref_sel cprset v cp v s gnd rset distribution reference refmon cp status ld p, p + 1 prescaler a/b counters n divider phase frequency detector lock detect charge pump pll reference hold 01 divide by 1, 2, 3, 4, 5, or 6 pd sync refin reset eeprom digital logic eeprom divide by 1 to 32 out0 out0 out1 out1 out2 out2 divide by 1 to 32 out3 out3 out4 out4 out5 out5 divide by 1 to 32 out6 out6 out7 out7 out8 out8 divide by 1 to 32 out9 out9 out10 out10 out11 out11 zero delay block lvpecl/cmos output status status sp1 sp0 spi interface i 2 c interface sclk/scl sdio/sda sdo cs serial port decode vs_drv optional 07239-031 figure 26. clock distribution or external vco < 1600 mhz (mode 1)
ad9520-5 rev. 0 | page 28 of 80 mode 2: high frequency clock distributionclk or external vco > 1600 mhz the ad9520 power-up default configuration has the pll powered off and the routing of the input set so that the clk/ clk input is connected to the distribution section through the vco divider (divide-by-1/divide-by-2/divide-by-3/divide-by-4/ divide-by-5/divide-by-6). this is a distribution-only mode that allows for an external input up to 2400 mhz (see ). the maximum frequency that can be applied to the channel dividers is 1600 mhz; therefore, higher input frequencies must be divided down before reaching the channel dividers. table 3 when the pll is enabled, this routing also allows the use of the pll with an external vco or vcxo with a frequency <2400 mhz. in this configuration, the external vco/vcxo feeds directly into the prescaler. the register settings shown in table 22 are the default values of these registers at power-up or after a reset operation. table 22. default register settin gs for clock dist ribution mode register description 0x010[1:0] = 01b pll asynchronous power-down (pll off ) 0x1e0[2:0] = 000b set vco divider = 2 0x1e1[0] = 0b use the vco divider when using the internal pll with an external vco, the pll must be turned on. table 23. settings when using an external vco register description 0x010[1:0] = 00b pll normal operation (pll on) 0x010 to 0x01e pll settings; select and enable a reference input; set r, n (p, a, b), pfd polarity, and i cp according to the intended loop configuration an external vco requires an external loop filter that must be connected between cp and the tuning pin of the vco. this loop filter determines the loop bandwidth and stability of the pll. make sure to select the proper pfd polarity for the vco being used. table 24. setting the pfd polarity register description 0x010[7] = 0b pfd polarity positive (higher control voltage produces higher frequency) 0x010[7] = 1b pfd polarity negative (higher control voltage produces lower frequency)
ad9520-5 rev. 0 | page 29 of 80 programmable n delay refin clk clk ref1 ref2 buf amp ad9520-5 r divider clock doubler status programmable r delay reference switchover ref_sel cprset v cp v s gnd rset distribution reference refmon cp status ld p, p + 1 prescaler a/b counters n divider phase frequency detector lock detect charge pump pll reference hold 01 divide by 1, 2, 3, 4, 5, or 6 pd sync refin reset eeprom digital logic eeprom divide by 1 to 32 out0 out0 out1 out1 out2 out2 divide by 1 to 32 out3 out3 out4 out4 out5 out5 divide by 1 to 32 out6 out6 out7 out7 out8 out8 divide by 1 to 32 out9 out9 out10 out10 out11 out11 zero delay block lvpecl/cmos output status status sp1 sp0 spi interface i 2 c interface sclk/scl sdio/sda sdo cs serial port decode vs_drv optional 07239-029 figure 27. high frequency clock distribution or external vco > 1600 mhz (mode 2)
ad9520-5 rev. 0 | page 30 of 80 phase-locked loop (pll) programmable n delay clk clk r divider clock doubler status programmable r delay cprset v cp v s gnd rset distribution reference refmon cp status ld p, p + 1 prescaler a/b counters n divider phase frequency detector lock detect charge pump pll reference hold 01 divide by 1, 2, 3, 4, 5, or 6 zero delay block from channel divider 0 vs_drv 07239-064 refin ref1 ref2 buf amp reference switchover ref_sel refin status status optional figure 28. pll functional block diagram the ad9520 includes on-chip pll blocks that can be used with an external vco or vcxo to create a complete phase-locked loop. the pll requires an external loop filter, which usually consists of a small number of capacitors and resistors. the configuration and components of the loop filter help to establish the loop bandwidth and stability of the pll. the ad9520 pll is useful for generating clock frequencies from a supplied reference frequency. this includes conversion of reference frequencies to much higher frequencies for subsequent division and distribution. in addition, the pll can be used to clean up jitter and phase noise on a noisy reference. the exact choice of pll parameters and loop dynamics is application specific. the flexibility and depth of the ad9520 pll allow the part to be tailored to function in many different applications and signal environments. configuration of the pll configuration of the pll is accomplished by programming the various settings for the r divider, n divider, pfd polarity, and charge pump current. the combination of these settings determines the pll loop bandwidth. these are managed through programmable register settings (see table 44 and table 48 ) and by the design of the external loop filter. successful pll operation and satisfactory pll loop performance are highly dependent on proper configuration of the pll settings, and the design of the external loop filter is crucial to the proper operation of the pll. adisimclk ? is a free program that can help with the design and exploration of the capabilities and features of the ad9520, including the design of the pll loop filter. the ad9516 model found in adisimclk version 1.2 can also be used for modeling the ad9520 loop filter. it is available at www.analog.com/clocks . phase frequency detector (pfd) the pfd takes inputs from the r divider and the n divider and produces an output proportional to the phase and frequency difference between them. the pfd includes a programmable delay element that controls the width of the antibacklash pulse. this pulse ensures that there is no dead zone in the pfd transfer function and minimizes phase noise and reference spurs. the antibacklash pulse width is set by 0x017[1:0]. an important limit to keep in mind is the maximum frequency allowed into the pfd. the maximum input frequency into the pfd is a function of the antibacklash pulse setting, as specified in the phase/frequency detector (pfd) parameter in tabl e 2 . charge pump (cp) the charge pump is controlled by the pfd. the pfd monitors the phase and frequency relationship between its two inputs and tells the cp to pump up or pump down to charge or discharge the integrating node (part of the loop filter). the integrated and filtered cp current is transformed into a voltage that drives the tuning node of the external vco to move the vco frequency up or down. the cp can be set (0x010[3:2]) for high impedance (allows holdover operation), for normal operation (attempts to lock the pll loop), for pump-up, or for pump-down (test modes). the cp current is programmable in eight steps from (nominally) 0.6 ma to 4.8 ma. the exact value of the cp current lsb is set by the cprset resistor, which is nominally 5.1 k.
ad9520-5 rev. 0 | page 31 of 80 pll external loop filter an example of an external loop filter for the pll is shown in figure 29 . a loop filter must be calculated for each desired pll configuration. the values of the components depend on the vco frequency, the k vco , the pfd frequency, the charge pump current, the desired loop bandwidth, and the desired phase margin. the loop filter affects the phase noise, the loop settling time, and the loop stability. a basic knowledge of pll theory is necessary for understanding loop filter design. adisimclk can help with the calculation of a loop filter according to the application requirements. clk/clk external vco/vcxo charge pump cp c1 c2 c3 r1 r2 ad9520-5 07239-065 figure 29. example of external loop filter for pll pll reference inputs the ad9520 features a flexible pll reference input circuit that allows a fully differential input, two separate single-ended inputs, or a 16.67 mhz to 33.33 mhz crystal oscillator with an on-chip maintaining amplifier. an optional reference clock doubler can be used to double the pll reference frequency. the input frequency range for the reference inputs is specified in table 2 . both the differential and the single-ended inputs are self-biased, allowing for easy ac coupling of input signals. either a differential or a single-ended reference must be specifically enabled. all pll reference inputs are off by default. the differential input and the single-ended inputs share two pins, refin (ref1) and refin (ref2). the desired reference input type is selected and controlled by 0x01c (see and ). table 44 table 48 when the differential reference input is selected, the self-bias level of the two sides is offset slightly to prevent chattering of the input buffer when the reference is slow or missing. the specification for this voltage level can be found in table 2 . the input hysteresis increases the voltage swing required of the driver to overcome the offset. the single-ended inputs can be driven by either a dc-coupled cmos level signal or an ac-coupled sine wave or square wave. to avoid input buffer chatter when a single-ended, ac-coupled input signal stops toggling, the user can set 0x018[7] to 1b. this shifts the dc offset bias point down 140 mv. to increase isolation and reduce power, each single-ended input can be independently powered down. the differential reference input receiver is powered down when the differential reference input is not selected or when the pll is powered down. the single-ended buffers power down when the pll is powered down or when their respective individual power-down registers are set. when the differential mode is selected, the single-ended inputs are powered down. in differential mode, the reference input pins are internally self- biased so that they can be ac-coupled via capacitors. it is possible to dc couple to these inputs. if the differential refin is driven by a single-ended signal, the unused side ( refin ) should be decoupled via a suitable capacitor to a quiet ground. shows the equivalent circuit of refin. figure 30 vs ref1 ref2 refin 150? 150? 10k ? 12k ? 10k ? 10k ? refin 85k ? v s 85k ? vs 07239-066 figure 30. refin equivalent circuit for non-xtal mode crystal mode is nearly identical to differential mode. the user enables a maintaining amplifier by setting the enable xtal osc bit, and putting a series resonant, at fundamental cut crystal across the refin/ refin pins. reference switchover the ad9520 supports dual single-ended cmos inputs, as well as a single differential reference input. in the dual single-ended reference mode, the ad9520 supports automatic and manual pll reference clock switching between ref1 (on pin refin) and ref2 (on pin refin ). this feature supports networking and other applications that require redundant references. the ad9520 features a dc offset option in single-ended mode. this option is designed to eliminate the risk of the reference inputs chattering when they are ac-coupled and the reference clock disappears. when using the reference switchover, the single-ended reference inputs should be dc-coupled cmos levels (with the ad9520 dc offset feature disabled). alternatively, the inputs can be ac-coupled and the dc offset feature enabled. the user should keep in mind, however, that the minimum input amplitude for the reference inputs is greater when the dc offset is turned on.
ad9520-5 rev. 0 | page 32 of 80 t here are several configurable modes of reference switchover. the switchover can be performed manually or automatically. manual switchover is performed either through register 0x01c or by using the ref_sel pin. the automatic switchover occurs when ref1 disappears. there is also a switchover deglitch feature which ensures that the pll does not receive rising edges that are far out of alignment with the newly selected reference. t here are two automatic reference switchover modes (0x01c): ? prefer ref1. switch from ref1 to ref2 when ref1 disappears. return to ref1 from ref2 when ref1 returns. ? stay on ref2. automatically switch to ref2 when ref1 disappears, but do not switch back to ref1 when it reappears. the reference can be set back to ref1 manually at an appropriate time. in automatic mode, ref1 is monitored by ref2. if ref1 disappears (two consecutive falling edges of ref2 without an edge transition on ref1), ref1 is considered missing. on the next subsequent rising edge of ref2, ref2 is used as the reference clock to the pll. if 0x01c[3] = 0b (default), when ref1 returns (four rising edges of ref1 without two falling edges of ref2 between the ref1 edges), the pll reference switches back to ref1. if 0x01c[3] = 1b, the user can control when to switch back to ref1. this is done by programming the part to manual reference select mode (0x01c[4] = 0b) and by ensuring that the registers and/or the ref_sel pin is set to select the desired reference. automatic mode can be reenabled when ref1 is reselected. manual switchover requires the presence of a clock on the reference input that is being switched to or that the deglitching feature be disabled (0x01c[7]). reference divider r the reference inputs are routed to the reference divider, r. r (a 14-bit counter) can be set to any value from 0 to 16,383 by writing to 0x011 and 0x012. (both r = 0 and r = 1 give divide-by-1.) the output of the r divider goes to one of the pfd inputs to be compared with the vco frequency divided by the n divider. the frequency applied to the pfd must not exceed the maximum allowable frequency, which depends on the antibacklash pulse setting (see tabl e 2 ). the r divider has its own reset. the r divider can be reset using the shared reset bit of the r, a, and b counters. it can also be reset by a sync operation. vco/vcxo feedback divider n: p, a, b, r the n divider is a combination of a prescaler (p) and two counters, a and b. the total divider value is n = ( p b ) + a where p can be 2, 4, 8, 16, or 32. prescaler the prescaler of the ad9520 allows for two modes of operation: a fixed divide (fd) mode of 1, 2, or 3, and a dual modulus (dm) mode where the prescaler divides by p and (p + 1) {2 and 3, 4 and 5, 8 and 9, 16 and 17, or 32 and 33}. the prescaler modes of operation are given in table 48 , 0x016[2:0]. not all modes are available at all frequencies (see tabl e 2 ). when operating the ad9520 in dual modulus mode, p/(p + 1), the equation used to relate the input reference frequency to the vco output frequency is f vco = ( f ref / r ) ( p b + a ) = f ref n / r however, when operating the prescaler in fd mode 1, fd mode 2, or fd mode 3, the a counter is not used (a = 0) and the equation simplifies to f vco = ( f ref / r ) ( p b ) = f ref n / r when a = 0, the divide is a fixed divide of p = 2, 4, 8, 16, or 32. by using combinations of dm and fd modes, the ad9520 can achieve values of n all the way down to n = 1. table 25 shows how a 10 mhz reference input can be locked to any integer multiple of n. note that the same value of n can be derived in different ways, as illustrated by the case of n = 12. the user can choose a fixed divide mode p = 2 with b = 6, use the dual modulus mode 2/3 with a = 0, b = 6, or use the dual modulus mode 4/5 with a = 0, b = 3. a and b counters the b counter must be 3 or bypassed, and unlike the r counter, a = 0 is actually zero. the maximum input frequency to the a/b counter is reflected in the maximum prescaler output frequency (~300 mhz) specified in table 2 . this is the prescaler input frequency (external vco or clk) divided by p. for example, dual modulus p = 8/9 mode is not allowed if the external vco frequency is greater than 2400 mhz because the frequency going to the a/b counter is too high. when the ad9520 b counter is bypassed (b = 1), the a counter should be set to zero, and the overall resulting divide is equal to the prescaler setting, p. the possible divide ratios in this mode are 1, 2, 3, 4, 8, 16, and 32. although manual reset is not normally required, the a/b counters have their own reset bit. alternatively, the a and b counters can be reset using the shared reset bit of the r, a, and b counters. note that these reset bits are not self-clearing. r, a, and b counters: sync pin reset the r, a, and b counters can be reset simultaneously through the sync pin. this function is controlled by 0x019[7:6] (see ). the table 48 sync pin reset is disabled by default.
ad9520-5 rev. 0 | page 33 of 80 r and n divider delays both the r and n dividers feature a programmable delay cell. these delays can be enabled to allow adjustment of the phase relationship between the pll reference clock and the vco or clk. each delay is controlled by three bits. the total delay range is about 1 ns. see 0x019 in table 2 and table 48 . digital lock detect (dld) by selecting the proper output through the mux on each pin, the dld function is available at the ld, status, and refmon pins. the digital lock detect circuit indicates a lock when the time difference of the rising edges at the pfd inputs is less than a specified value (the lock threshold). the loss of a lock is indicated when the time difference exceeds a specified value (the unlock threshold). note that the unlock threshold is wider than the lock threshold, which allows some phase error in excess of the lock window to occur without chattering on the lock indicator. the lock detect window timing depends on the value of the cprset resistor, as well as three settings: the digital lock detect window bit (0x018[4]), the antibacklash pulse width bit (0x017[1:0], see tabl e 2 ), and the lock detect counter (0x018[6:5]). the lock and unlock detection values in table 2 are for the nominal value of cprset = 5.11 k. doubling the cprset value to 10 k doubles the values in table 2 . a lock is not indicated until there is a programmable number of consecutive pfd cycles with a time difference less than the lock detect threshold. the lock detect circuit continues to indicate a lock until a time difference greater than the unlock threshold occurs on a single subsequent cycle. for the lock detect to work properly, the period of the pfd frequency must be greater than the unlock threshold. the number of consecutive pfd cycles required for a lock is programmable (0x018[6:5]). note that it is possible in certain low (<500 hz) loop bandwidth, high phase margin cases that the dld can chatter during acqui- sition, which can cause the ad9520 to automatically enter and exit holdover. to avoid this problem, it is recommended that the user make provisions for a capacitor to ground on the ld pin so that current source digital lock detect (csdld) mode can be used. table 25. how a 10 mhz reference input can be locked to any integer multiple of n f ref (mhz) r p a b n f vco (mhz) mode notes 10 1 1 x 1 1 1 10 fd p = 1, b = 1 (bypassed) 10 1 2 x 1 1 2 20 fd p = 2, b = 1 (bypassed) 10 1 1 x 1 3 3 30 fd p = 1, b = 3 10 1 1 x 1 4 4 40 fd p = 1, b = 4 10 1 1 x 1 5 5 50 fd p = 1, b = 5 10 1 2 x 1 3 6 60 fd p = 2, b = 3 10 1 2 0 3 6 60 dm p and p + 1 = 2 and 3, a = 0, b = 3 10 1 2 1 3 7 70 dm p and p + 1 = 2 and 3, a = 1, b = 3 10 1 2 2 3 8 80 dm p and p + 1 = 2 and 3, a = 2, b = 3 10 1 2 1 4 9 90 dm p and p + 1 = 2 and 3, a = 1, b = 4 10 1 2 x 1 5 10 100 fd p = 2, b = 5 10 1 2 0 5 10 100 dm p and p + 1 = 2 and 3, a = 0, b = 5 10 1 2 1 5 11 110 dm p and p + 1 = 2 and 3, a = 1, b = 5 10 1 2 x 1 6 12 120 fd p = 2, b = 6 10 1 2 0 6 12 120 dm p and p + 1 = 2 and 3, a = 0, b = 6 10 1 4 0 3 12 120 dm p and p + 1 = 4 and 5, a = 0, b = 3 10 1 4 1 3 13 130 dm p and p + 1 = 4 and 5, a = 1, b = 3 1 x = dont care.
ad9520-5 rev. 0 | page 34 of 80 a nalog lock detect (ald) t he ad9520 provides an ald function that can be selected for use at the ld pin. there are two operating modes for ald: ? n-channel open-drain lock detect. this signal requires a pull-up resistor to the positive supply, vs. the output is normally high with short, low going pulses. lock is indicated by the minimum duty cycle of the low going pulses. ? p-channel open-drain lock detect. this signal requires a pull-down resistor to gnd. the output is normally low with short, high going pulses. lock is indicated by the minimum duty cycle of the high going pulses. the analog lock detect function requires an rc filter to provide a logic level indicating lock/unlock. the adisimclk tool can be used to help the user select the right passive component values for ald to ensure its correct operation. ad9520 ald ld r1 c v out r2 v s = 3.3v 07239-067 figure 31. example of analog lock detect filter using n-channel open-drain driver current source digital lock detect (csdld) during the pll locking sequence, it is normal for the dld signal to toggle a number of times before remaining steady when the pll is completely locked and stable. there may be applications where it is desirable to have dld asserted only after the pll is solidly locked. this is possible by using the current source digital lock detect function. t he current source lock detect provides a current of 110 a when dld is true and shorts to ground when dld is false. if a capacitor is connected to the ld pin, it charges at a rate determined by the current source during the dld true time but is discharged nearly instantly when dld is false. by monitoring the voltage at the ld pin (top of the capacitor), ld = high happens only after the dld is true for a sufficiently long time. any momentary dld false resets the charging. by selecting a properly sized capacitor, it is possible to delay a lock detect indication until the pll is stably locked and the lock detect does not chatter. t o use current source digital lock detect, do the following: ? place a capacitor to ground on the ld pin ? set 0x01a[5:0] = 0x04 ? enable the ld pin comparator (0x01d[3] = 1) the ld pin comparator senses the voltage on the ld pin, and the comparator output can be made available at the refmon pin control (0x01b[4:0]) or the status pin control (0x017[7:2]). the internal ld pin comparator trip point and hysteresis are given in table 14 . the voltage on the capacitor can also be sensed by an external comparator connected to the ld pin. in this case, enabling the on-board ld pin comparator is not necessary. the user can asynchronously enable individual clock outputs only when csdld is high. to enable this feature, set the appropriate bits in the enable output on the csdld registers (0x0fc and 0x0fd). ad9520 ld refmon or status c v out 110a dld ld pin comparator 07239-068 figure 32. current source digital lock detect external vcxo/vco clock input (clk/ clk ) this differential input is used to drive the ad9520 clock distribution section. this input can receive up to 2.4 ghz. the pins are internally self-biased, and the input signal should be ac-coupled via capacitors. vs clock input stage c lk c lk 5k? 5k? 2.5k ? 2.5k ? 07239-032 figure 33. clk equivalent input circuit the clk/ clk input can be used either as a distribution only input (with the pll off) or as a feedback input for an external vco/vcxo using the internal pll. holdover the ad9520 pll has a holdover function. holdover is implemented by placing the charge pump in a high impedance state. this function is useful when the pll reference clock is lost. holdover mode allows the external vco to maintain a relatively constant frequency even though there is no reference clock. without this function, the charge pump is placed into a constant pump-up or pump-down state, resulting in a massive vco frequency shift. because the charge pump is placed in a high impedance state, any leakage that occurs at the charge pump output or the vco tuning node causes a drift of the vco frequency. this can be mitigated by using a loop filter that contains a large capacitive component because this drift is limited by the current leakage induced slew rate (i leak /c) of the vco control voltage. both a manual holdover mode, using the sync pin, and an automatic holdover mode are provided. to use either function, the holdover function must be enabled (0x01d[0]).
ad9520-5 rev. 0 | page 35 of 80 external/manual holdover mode a manual holdover mode can be enabled that allows the user to place the charge pump into a high impedance state when the sync pin is asserted low. this operation is edge sensitive, not level sensitive. the charge pump enters a high impedance state immediately. to take the charge pump out of a high impedance state, take the sync pin high. the charge pump then leaves the high impedance state synchronously with the next pfd rising edge from the reference clock. this prevents extraneous charge pump events from occurring during the time between sync going high and the next pfd event. this also means that the charge pump stays in a high impedance state if there is no reference clock present. the b counter (in the n divider) is reset synchronously with the charge pump, leaving the high impedance state on the reference path pfd event. this helps align the edges out of the r and n dividers for faster settling of the pll. because the prescaler is not reset, this feature works best when the b and r numbers are close because this results in a smaller phase difference for the loop to settle out. when using this mode, the channel dividers should be set to ignore the sync pin (at least after an initial sync event). if the dividers are not set to ignore the sync pin, any time sync is taken low to put the part into holdover, the distribution outputs turn off. the channel divider ignore sync function is found in 0x191[6], 0x194[6], 0x197[6], and 0x19a[6] for channel divider 0, channel divider 1, channel divider 2, and channel divider 3, respectively. automatic/internal holdover mode when enabled, this function automatically puts the charge pump into a high impedance state when the loop loses lock. the assumption is that the only reason the loop loses lock is due to the pll losing the reference clock; therefore, the holdover function puts the charge pump into a high impedance state to maintain the vco frequency as close as possible to the original frequency before the reference clock disappeared. a flowchart of the automatic/internal holdover function operation is shown in figure 34 .
ad9520-5 rev. 0 | page 36 of 80 no no no no yes yes yes yes yes pll enabled dld == low was ld pin == high when dld went low? high impedance charge pump reference edge at pfd? release charge pump high impedance dld == high loop out of lock. digital lock detect signal goes low when the loop leaves lock as determined by the phase difference at the input of the pfd. analog lock detect pin indicates lock was previously achieved. (0x01d[3] = 1; use ld pin voltage with holdover. 0x01d[3] = 0; ignore ld pin voltage, treat ld pin as always high.) charge pump is made high impedance. pll counters continue operating normally. charge pump remains high impedance until the reference returns. take charge pump out of high impedance. pll can now resettle. wait for dld to go high. this takes 5 to 255 cycles (programming of the dld delay counter) with the reference and feedback clocks inside the lock window at the pfd. this ensures that the holdover function waits for the pll to settle and lock before the holdover function can be retriggered. yes 0 7239-069 figure 34. flowchart of automatic/internal holdover mode the holdover function senses the logic level of the ld pin as a condition to enter holdover. the signal at ld can be from the dld, ald, or current source ld mode (csdld). it is possible to disable the ld comparator (0x01d[3]), which causes the holdover function to always sense ld as being high. if dld is used, it is possible for the dld signal to chatter while the pll is reacquiring lock. the holdover function may retrigger, thereby preventing the holdover mode from terminating. use of the current source lock detect mode is recommended to avoid this situation (see the current source digital lock detect (csdld) section). when in holdover mode, the charge pump stays in a high impedance state as long as there is no reference clock present. as in the external holdover mode, the b counter (in the n divider) is reset synchronously with the charge pump leaving the high impedance state on the reference path pfd event. this helps align the edges out of the r and n dividers for faster settling of the pll and reduces frequency errors during settling. because the prescaler is not reset, this feature works best when the b and r numbers are close because this results in a smaller phase difference for the loop to settle out.
ad9520-5 rev. 0 | page 37 of 80 after leaving holdover, the loop then reacquires lock, and the ld pin must go high (if 0x01d[3] = 1) before it can reenter holdover. t he holdover function always responds to the state of the currently selected reference (0x01c). if the loop loses lock during a reference switchover (see the reference switchover section), holdover is triggered briefly until the next reference clock edge at the pfd. t he following registers affect the automatic/internal holdover function: ? 0x018[6:5]lock detect counter. this changes how many consecutive pfd cycles with edges inside the lock detect window are required for the dld indicator to indicate lock. this impacts the time required before the ld pin can begin to charge as well as the delay from the end of a holdover event until the holdover function can be reengaged. ? 0x018[3]disable digital lock detect. this bit must be set to 0 to enable the dld circuit. internal/automatic holdover does not operate correctly without the dld function enabled. ? 0x01a[5:0]lock detect pin control. set this to 000100b to put it in the current source lock detect mode if using the ld pin comparator. load the ld pin with a capacitor of an appropriate value. ? 0x01d[3]ld pin comparator enable. 1 = enable; 0 = disable. when disabled, the holdover function always senses the ld pin as high. ? 0x01d[1]external holdover control. ? 0x01d[0]holdover enable. if holdover is disabled, both external and automatic internal holdover are disabled. f or example, if the user wants to configure automatic holdover with ? automatic reference switchover, prefer ref1. ? digital lock detect: five pfd cycles, high range window. ? automatic holdover using the ld pin comparator. t he following registers are set (in addition to the normal pll registers): ? 0x018[6:5] = 00b; lock detect counter = five cycles. ? 0x018[4] = 0b; digital lock detect window = high range. ? 0x018[3] = 1b; disable dld normal operation. ? 0x01a[5:0] = 000100b; program ld pin control to current source lock detect mode. ? 0x01c[4] = 1b; enable automatic switchover. ? 0x01c[3] = 0b; prefer ref1. ? 0x01c[2:1] = 11b; enable ref1 and ref2 input buffers. ? 0x01d[3] = 1b; enable ld pin comparator. ? 0x01d[1] = 0b; disable external holdover mode and use automatic/internal holdover mode. ? 0x01d[0] = 1b; enable holdover. frequency status monitors the ad9520 contains three frequency status monitors that are used to indicate if the pll reference (or references in the case of single-ended mode) and the vco have fallen below a threshold frequency. a diagram showing their location in the pll is shown in figure 35 . the pll reference monitors have two threshold frequencies: normal and extended (see tabl e 14 ). the reference frequency monitor thresholds are selected in 0x01f. programmable n delay clk clk ref1 ref2 buf status status r divider clock doubler clk frequency status programmable r delay reference switchover ref_sel cprset v cp v s gnd rset distribution reference refmon cp status ld p, p + 1 prescaler a/b counters n divider phase frequency detector lock detect charge pump pll reference hold 01 divide by 1, 2, 3, 4, 5, or 6 zero delay block from channel divider 0 vs_drv refin optional refin 07239-070 figure 35. reference and vco status monitors
ad9520-5 rev. 0 | page 38 of 80 divide by 1, 2, 3, 4, 5, or 6 external vcxo clk/clk r divider r delay n divider n delay pfd cp mux1 reg 0x01e[1] = 1 01 refin/ refin internal zero delay clock feedback path channel divider 0 channel divider 1 channel divider 2 channel divider 3 out0 to out2 out3 to out5 out6 to out8 out9 to out11 ad9520-5 07239-053 loop filter figure 36. zero delay function zero delay operation zero delay operation aligns the phase of the output clocks with the phase of the external pll reference input. the zero delay function of the ad9520-5 is achieved by feeding the output of channel divider 0 back to the pll n divider. in figure 36 , the change in signal routing for zero delay mode is shown in blue. set register 0x01e[1] = 1b to select zero delay mode. in the zero delay mode, the output of channel divider 0 is routed back to the pll (n divider) through mux1 (feedback path shown in blue in figure 36 ). the pll synchronizes the phase/edge of the output of channel divider 0 with the phase/edge of the reference input. because the channel dividers are synchronized to each other, the outputs of the channel divider are synchronous with the reference input. both the r delay and the n delay inside the pll can be programmed to compensate for the propagation delay from the output drivers and pll components to minimize the phase offset between the clock output and the reference input to achieve zero delay.
ad9520-5 rev. 0 | page 39 of 80 mode 1 (clock distribution mode) distribution clock mode 2 (hf clock distribution mode) clk clk 01 divide by 1, 2, 3, 4, 5, or 6 clock distri- bution pll clk clk 01 divide by 1, 2, 3, 4, 5, or 6 clock distri- bution pll distribution clock 07239-054 figure 37. simplified diagram of the two clock distribution operation modes clock distribution a clock channel consists of three lvpecl clock outputs or six cmos clock outputs that share a common divider. a clock output consists of the drivers that connect to the output pins. the clock outputs have either lvpecl or cmos at the pins. the ad9520 has four clock channels. each channel has its own programmable divider that divides the clock frequency applied to its input. the channel dividers can divide by any integer from 1 to 32. the ad9520 features a vco divider that divides the clk input by 1, 2, 3, 4, 5, or 6 before going to the individual channel dividers. the vco divider has two purposes. the first is to limit the maximum input frequency of the channel dividers to 1.6 ghz. the other is to allow the ad9520 to generate even lower frequencies than would be possible with only a simple post divider. the channel dividers allow for a selection of various duty cycles, depending on the currently set division. that is, for any specific division, d, the output of the divider can be set to high for n + 1 input clock cycles and low for m + 1 input clock cycles (where d = n + m + 2). for example, a divide-by-5 can be high for one divider input cycle and low for four cycles, or a divide-by-5 can be high for three divider input cycles and low for two cycles. other combinations are also possible. the channel dividers include a duty-cycle correction function that can be disabled. in contrast to the selectable duty cycle just described, this function can correct a non-50% duty cycle caused by an odd division. however, this requires that the division be set by m = n + 1. in addition, the channel dividers allow a coarse phase offset or delay to be set. depending on the division selected, the output can be delayed by up to 15 input clock cycles. for example, if the frequency at the input of the channel divider is 1 ghz, the channel divider output can be delayed by up to 15 ns. the divider outputs can also be set to start high or to start low. operation modes there are two clock distribution operating modes, and these are shown in figure 37 . it is not necessary to use the vco divider if the clk frequency is less than the maximum channel divider input frequency (1600 mhz); otherwise, the vco divider must be used to reduce the frequency going to the channel dividers. table 26 shows how the operation modes are selected. 0x1e1[0] selects the channel divider source. table 26. operation modes mode 0x1e1[0] vco divider 2 0 used 1 1 not used clk direct-to-lvpecl outputs it is possible to connect the clk directly to the lvpecl outputs. however, the lvpecl outputs may not be able to meet the v od specification in table 4 above 1600 mhz. to connect the lvpecl outputs directly to the clk input, the user must select the vco divider as the source to the distribution section, even if no channel uses it. table 27. routing vco divider input directly to the outputs register setting selection 0x1e1[0] = 0b clk is the source; vco divider selected 0x192[1] = 1b direct-to-output out0, out1, out2 0x195[1] = 1b direct-to-output out3, out4, out5 0x198[1] = 1b direct-to-output out6, out7, out8 0x19b[1] = 1b direct-to-output out9, out10, out11
ad9520-5 rev. 0 | page 40 of 80 clock frequency division the total frequency division is a combination of the vco divider (when used) and the channel divider. when the vco divider is used, the total division from the clk to the output is the product of the vco divider (1, 2, 3, 4, 5, and 6) and the division of the channel divider. table 28 indicates how the frequency division for a channel is set. table 28. frequency division vco divider setting 1 channel divider setting clk direct- to-output setting resulting frequency division 1 to 6 dont care enable 1 1 to 6 2 to 32 disable (1 to 6) (2 to 32) 2 to 6 bypass disable (2 to 6) (1) 1 bypass disable output static (illegal state) vco divider bypassed bypass dont care 1 vco divider bypassed 2 to 32 dont care 2 to 32 1 the bypass vco divider (0x1e1[0] = 1) is not the same as vco divider = 1. the channel dividers feeding the output drivers contain one 2-to-32 frequency divider. this divider provides for division-by-1 to division-by-32. division-by-1 is accomplished by bypassing the divider. the dividers also provide for a programmable duty cycle, with optional duty-cycle correction when the divide ratio is odd. a phase offset or delay in increments of the input clock cycle is selectable. the channel dividers operate with a signal at their inputs up to 1600 mhz. the features and settings of the dividers are selected by programming the appropriate setup and control registers (see table 44 through table 55 ). vco divider the vco divider provides frequency division between the clk input and the clock distribution channel dividers. the vco divider can be set to divide by 1, 2, 3, 4, 5, or 6 (see tabl e 51 , 0x1e0[2:0]). however, when the vco divider is set to 1, none of the channel output dividers can be bypassed. the vco divider can also be set to static, which is useful for applications where the only desired output frequency is the clk input frequency. making the vco divider static increases the wide band spurious-free dynamic range (sfdr). an alternative to achieving the same sfdr performance is to set the vco divider to 1 and enable clk direct mode. channel dividers a channel divider drives each group of three lvpecl outputs. there are four channel dividers (0, 1, 2, and 3) driving 12 lvpecl outputs (out0 to out11). table 29 gives the register locations used for setting the division and other functions of these dividers. the division is set by the values of m and n. the divider can be bypassed (equivalent to divide-by-1, divider circuit is powered down) by setting the bypass bit. the duty-cycle correction can be enabled or disabled according to the setting of the disable divider dcc bits. table 29. setting d x for the output dividers divider low cycles m high cycles n bypass disable div dcc 0 0x190[7:4] 0x190[3:0] 0x191[7] 0x192[0] 1 0x193[7:4] 0x193[3:0] 0x194[7] 0x195[0] 2 0x196[7:4] 0x196[3:0] 0x197[7] 0x198[0] 3 0x199[7:4] 0x199[3:0] 0x19a[7] 0x19b[0] channel frequency division (0, 1, 2, and 3) for each channel (where the channel number x is 0, 1, 2, or 3), the frequency division, d x , is set by the values of m and n (four bits each, representing decimal 0 to decimal 15), where number of low cycles = m + 1 number of high cycles = n + 1 the high and low cycles are cycles of the clock signal currently routed to the input of the channel dividers (vco divider out or clk). when a divider is bypassed, d x = 1. otherwise, d x = (n + 1) + (m + 1) = n + m + 2. this allows each channel divider to divide by any integer from 1 to 32. d uty cycle and duty-cycle correction t he duty cycle of the clock signal at the output of a channel is a result of some or all of the following conditions: ? the m and n values for the channel ? dcc enabled/disabled ? vco divider enabled/bypassed ? the clk input duty cycle the dcc function is enabled by default for each channel divider. however, the dcc function can be disabled individually for each channel divider by setting the disable divider dcc bit for that channel. c ertain m and n values for a channel divider result in a non- 50% duty cycle. a non-50% duty cycle can also result with an even division, if m n. the duty-cycle correction function automatically corrects non-50% duty cycles at the channel divider output to 50% duty cycle. d uty-cycle correction requires the following channel divider conditions: ? an even division must be set as m = n. ? an odd division must be set as m = n + 1. when not bypassed or corrected by the dcc function, the duty cycle of each channel divider output is the numerical value of (n + 1)/(n + m + 2) expressed as a percent.
ad9520-5 rev. 0 | page 41 of 80 the duty cycle at the output of the channel divider for various configurations is shown in tabl e 30 to table 33 . table 30. channel divider output duty cycle with vco divider 1; input duty cycle is 50% vco divider d x output duty cycle n + m + 2 disable div dcc = 1 disable div dcc = 0 even channel divider bypassed 50% 50% odd = 3 channel divider bypassed 33.3% 50% odd = 5 channel divider bypassed 40% 50% even, odd even (n + 1)/(n + m + 2) 50%, requires m = n even, odd odd (n + 1)/(n + m + 2) 50%, requires m = n + 1 table 31. channel divider output duty cycle with vco divider 1; input duty cycle is x% vco divider d x output duty cycle n + m + 2 disable div dcc = 1 disable div dcc = 0 even channel divider bypassed 50% 50% odd = 3 channel divider bypassed 33.3% (1 + x%)/3 odd = 5 channel divider bypassed 40% (2 + x%)/5 even even (n + 1)/ (n + m + 2) 50%, requires m = n even odd (n + 1)/ (n + m + 2) 50%, requires m = n + 1 odd = 3 even (n + 1)/ (n + m + 2) 50%, requires m = n odd = 3 odd (n + 1)/ (n + m + 2) (3n + 4 + x%)/(6n + 9), requires m = n + 1 odd = 5 even (n + 1)/ (n + m + 2) 50%, requires m = n odd = 5 odd (n + 1)/ (n + m + 2) (5n + 7 + x%)/(10n + 15), requires m = n + 1 table 32. channel divider output duty cycle when the vco divider is enabled and set to 1 input clock duty cycle d x output duty cycle n + m + 2 disable div dcc = 1 disable div dcc = 0 any even (n + 1)/ (m + n + 2) 50%, requires m = n 50% odd (n + 1)/ (m + n + 2) 50%, requires m = n + 1 x% odd (n + 1)/ (m + n + 2) (n + 1 + x%)/(2 n + 3), requires m = n + 1 note that the channel divider must be enabled when the vco divider = 1. table 33. channel divider output duty cycle when the vco divider is bypassed input clock duty cycle d x output duty cycle n + m + 2 disable div dcc = 1 disable div dcc = 0 any channel divider bypassed same as input duty cycle same as input duty cycle any even (n + 1)/ (m + n + 2) 50%, requires m = n 50% odd (n + 1)/ (m + n + 2) 50%, requires m = n + 1 x% odd (n + 1)/ (m + n + 2) (n + 1 + x%)/(2 n + 3), requires m = n + 1 if the clk input is routed directly to the output, the duty cycle of the output is the same as the clk input. phase offset or coarse time delay each channel divider allows for a phase offset, or a coarse time delay, to be programmed by setting register bits (see table 34 ). these settings determine the number of cycles (successive rising edges) of the channel divider input frequency by which to offset, or delay, the rising edge of the output of the divider. this delay is with respect to a nondelayed output (that is, with a phase offset of zero). the amount of the delay is set by five bits loaded into the phase offset (po) register plus the start high (sh) bit for each channel divider. when the start high bit is set, the delay is also affected by the number of low cycles (m) programmed for the divider. it is necessary to use the sync function to make phase offsets effective (see the synchronizing the outputs function section). table 34. setting phase offset and division divider start high (sh) phase offset (po) low cycles m high cycles n 0 0x191[4] 0x191[3:0] 0x190[7:4] 0x190[3:0] 1 0x194[4] 0x194[3:0] 0x193[7:4] 0x193[3:0] 2 0x197[4] 0x197[3:0] 0x196[7:4] 0x196[3:0] 3 0x19a[4] 0x19a[3:0] 0x199[7:4] 0x199[3:0]
ad9520-5 rev. 0 | page 42 of 80 let t = delay (in seconds). c = delay (in cycles of clock signal at input to d x ). t x = period of the clock signal at the input of the divider, d x (in seconds). = 16 sh[4] + 8 po[3] + 4 po[2] + 2 po[1] + 1 po[0] ? synchronization of the outputs can be executed as part of the chip power-up sequence. ? the reset pin is forced low and then released (chip reset). ? the pd pin is forced low and then released (chip power-down). the most common way to execute the sync function is to use the sync pin to perform a manual synchronization of the outputs. this requires a low going signal on the sync pin, which is held low and then released when synchronization is desired. the timing of the sync operation is shown in (using the vco divider) and in (the vco divider is not used). there is an uncertainty of up to one cycle of the clock at the input to the channel divider due to the asynchronous nature of the sync signal with respect to the clock edges inside the ad9520. figure 39 figure 40 the channel divide by is set as n = high cycles and m = low cycles. case 1 for 15, t = t x c = t / t x = the pipeline delay from the sync rising edge to the beginning of the synchronized output clocking is between 14 cycles and 15 cycles of clock at the channel divider input, plus either one cycle of the vco divider input (see ) or one cycle of the channel divider input (see ), depending on whether the vco divider is used. cycles are counted from the rising edge of the signal. in addition, there is an additional 1.2 ns (typical) delay from the sync signal to the internal synchronization logic, as well as the propagation delay of the output driver. the driver propagation delay is approximately 100 ps for the lvpecl driver and approximately 1.5 ns for the cmos driver. figure 39 figure 40 case 2 for 16, t = ( ? 16 + m + 1) t x c = t / t x by giving each divider a different phase offset, output-to-output delays can be set in increments of the channel divider input clock cycle. figure 38 shows the results of setting such a coarse offset between outputs. 0 1 2 3 4 5 6 7 8 9 101112131415 tx divider 0 divider 1 divider 2 channel divider input sh = 0 po = 0 sh = 0 po = 1 sh = 0 po = 2 1 tx 2 tx channel divider outputs div = 4, duty = 50% 07239-071 another common way to execute the sync function is by setting and resetting the soft sync bit at 0x230[0]. both setting and resetting of the soft sync bit require an update all registers (0x232[0] = 1b) operation to take effect. a sync operation brings all outputs that have not been excluded (by the ignore sync bit) to a preset condition before allowing the outputs to begin clocking in synchronicity. the preset condition takes into account the settings in each of the channels start high bit and its phase offset. these settings govern both the static state of each output when the sync operation is happening and the state and relative phase of the outputs when they begin clocking again upon completion of the sync operation. between outputs and after synchronization, this allows for the setting of phase offsets. figure 38. effect of coarse phase offset (or delay) synchronizing the outputs sync function the ad9520 clock outputs can be synchronized to each other. outputs can be individually excluded from synchronization. synchronization consists of setting the nonexcluded outputs to a preset set of static conditions. these conditions include the divider ratio and phase offsets for a given channel divider. this allows the user to specify different divide ratios and phase offsets for each of the four channel dividers. releasing the sync pin allows the outputs to continue clocking with the preset conditions applied. the ad9520 differential lvpecl outputs are four groups of three, sharing a channel divider per triplet. in the case of cmos, each lvpecl differential pair can be configured as two single- ended cmos outputs. the synchronization conditions apply to all of the drivers that belong to that channel divider. each channel (a divider and its outputs) can be excluded from any sync operation by setting the ignore sync bit of the channel. channels that are set to ignore sync (excluded channels) do not set their outputs static during a sync operation, and their outputs are not synchronized with those of the included channels. synchronization of the outputs is executed in the following ways: ? the sync pin is forced low and then released (manual sync). ? by setting and then resetting any one of the following three bits: the soft sync bit (0x230[0]), the soft reset bit (0x000[5] [mirrored]), and the power-down distribution reference bit (0x230[1]).
ad9520-5 rev. 0 | page 43 of 80 1234567 8 910 input to vco divider input to channel divider output of channel divider s ync pin 1 11 12 13 14 14 to 15 cycles at channel divider input + 1 cycle at vco divider input channel divider output static channel divide r output clocking channel divide r output clocking 07239-073 figure 39. sync timing pipeline delay when vco divider is used input to clk input to channel divide r output of channel divider sync pin 14 to 15 cycles at channel divider input + 1 cycle at clk input 1234567 8 910 11 12 13 14 1 channel divider output static channel divide r output clocking channel divider output clocking 0 7239-074 figure 40. sync timing pipeline delay when vco divider is not used lvpecl output drivers the lvpecl differential voltage (v od ) is selectable (from ~400 mv to 960 mv, see bit 1 and bit 2 in register 0x0f0 to register 0x0fb). the lvpecl outputs have dedicated pins for power supply (vs_drv), allowing a separate power supply to be used. vs_drv can be from 2.5 v or from 3.3 v. the lvpecl output polarity can be set as noninverting or inverting, which allows for the adjustment of the relative polarity of outputs within an application without requiring a board layout change. each lvpecl output can be powered down or powered up as needed. because of the architecture of the lvpecl output stages, there is the possibility of electrical overstress and breakdown under certain power-down conditions. for this reason, the lvpecl outputs have two power-down modes: total power-down and safe power-down. in total power-down mode, all output drivers are shut off simultaneously. this mode must not be used if there is an external voltage bias network (such as thevenin equivalent termination) on the output pins that will cause a dc voltage to appear at the powered down outputs. however, total power- down mode is allowed when the lvpecl drivers are terminated using only pull-down resistors. the total power-down mode is activated by setting 0x230[1]. the primary power-down mode is the safe power-down mode. this mode continues to protect the output devices while powered down. there are three ways to activate safe power- down mode: individually set the power-down bit for each driver, power down an individual output channel (all of the drivers associated with that channel are powered down automatically), and activate sleep mode.
ad9520-5 rev. 0 | page 44 of 80 r2 200? r1 200 ? sw1b sw1a sw2 qn2 qn1 n2 n1 out out 4.4ma 07239-058 figure 41. lvpecl output simplified equivalent circuit cmos output drivers the user can also individually configure each lvpecl output as a pair of cmos outputs, which provides up to 24 cmos outputs. when an output is configured as cmos, cmos output a and cmos output b are automatically turned on. for a given differential pair, either cmos output a or output b can be turned on or off independently. the user can also select the relative polarity of the cmos outputs for any combination of inverting and noninverting (see register 0x0f0 to register 0x0fb). the user can power down each cmos output as needed to save power. the cmos output power-down is individually controlled by the enable cmos output register (0x0f0[6:5] to 0x0fb[6:5]). the cmos driver is in tristate when it is powered down. out1/ out1 v s_drv 07239-035 figure 42. cmos equiva lent output circuit reset modes the ad9520 has a power-on reset (por) and several other ways to apply a reset condition to the chip. power-on reset during chip power-up, a power-on reset pulse is issued when vs reaches ~2.6 v (<2.8 v) and restores the chip either to the setting stored in eeprom (with the eeprom pin = 1) or to the on-chip setting (with the eeprom pin = 0). at power-on, the ad9520 also executes a sync operation, which brings the outputs into phase alignment according to the default settings. the output drivers are held in sync for the duration of the internally generated power-up sync timer (~70 ms). the outputs begin to toggle after this period. hardware reset via the reset pin reset , a hard reset (an asynchronous hard reset is executed by briefly pulling reset low), restores the chip either to the setting stored in eeprom (the eeprom pin = 1) or to the on-chip setting (the eeprom pin = 0). a hard reset also executes a sync operation, which brings the outputs into phase alignment according to the default settings. when eeprom is inactive (the eeprom pin = 0), it takes ~2 s for the outputs to begin toggling after reset is issued. when eeprom is active (the eeprom pin = 1), it takes ~20 ms for the outputs to toggle after reset is brought high. soft reset via the serial port the serial port control register allows for a soft reset by setting bit 2 and bit 5 in register 0x000. when bit 5 and bit 2 are set, the chip enters a soft reset mode and restores the chip either to the setting stored in eeprom (the eeprom pin = 1) or to the on-chip setting (the eeprom pin = 0), except for register 0x000. except for the self-clearing bits, bit 2 and bit 5, register 0x000 retains its previous value prior to reset. during the internal reset, the outputs hold static. these bits are self-clearing. however, the self-clearing operation does not complete until an additional serial port sclk cycle, and the ad9520 is held in reset until that happens. soft reset to settings in eeprom when eeprom pin = 0 via the serial port the serial port control register allows the chip to be reset to settings in eeprom when the eeprom pin = 1 via 0xb02[1]. this bit is self-clearing. this bit does not have any effect when the eeprom pin = 0. it takes ~20 ms for the outputs to begin toggling after the soft_eeprom register is cleared. power-down modes chip power-down via pd the ad9520 can be put into a power-down condition by pulling the pd pin low. power-down turns off most of the functions and currents inside the ad9520. the chip remains in this power-down state until pd is brought back to logic high. when taken out of power-down mode, the ad9520 returns to the settings programmed into its registers prior to the power-down, unless the registers are changed by new programming while the pd pin is held low. powering down the chip shuts down the currents on the chip, except for the bias current necessary to maintain the lvpecl outputs in a safe shutdown mode. the lvpecl bias currents are needed to protect the lvpecl output circuitry from damage that can be caused by certain termination and load configurations when tristated. because this is not a complete power-down, it can be called sleep mode. the ad9520 contains special circuitry to prevent runt pulses on the outputs when the chip is entering or exiting sleep mode.
ad9520-5 rev. 0 | page 45 of 80 w hen the ad9520 is in a pd power-down, the chip is in the following state: ? the pll is off (asynchronous power-down). ? the clk input buffer is off, but the clk input dc bias circuit is on. ? in differential mode, the reference input buffer is off, but the dc bias circuit is still on. ? in singled-ended mode, the reference input buffer is off, and the dc bias circuit is off. ? all dividers are off. ? all cmos outputs are tristated. ? all lvpecl outputs are in safe off mode. ? the serial control port is active, and the chip responds to commands. pll power-down the pll section of the ad9520 can be selectively powered down. there are two pll power-down modes set by register 0x010[1:0]: asynchronous and synchronous. in asynchronous power-down mode, the device powers down as soon as the registers are updated. in synchronous power-down mode, the pll power-down is gated by the charge pump to prevent unwanted frequency jumps. the device goes into power- down on the occurrence of the next charge pump event after the registers are updated. distribution power-down the distribution section can be powered down by writing 0x230[1] = 1b, which turns off the bias to the distribution section. if the lvpecl power-down mode is normal operation (0b), it is possible for a low impedance load on that lvpecl output to draw significant current during this power-down. if the lvpecl power-down mode is set to 1b, the lvpecl output is not protected from reverse bias and can be damaged under certain termination conditions. individual clock output power-down any of the clock distribution outputs can be powered down into safe power-down mode by individually writing to the appropriate registers. the register map details the individual power-down settings for each output. these settings are found in register 0x0f0[0] to register 0x0fb[0]. individual clock channel power-down any of the clock distribution channels can be powered down individually by writing to the appropriate registers. powering down a clock channel is similar to powering down an individual driver, but it saves more power because the dividers are also powered down. powering down a clock channel also automatically powers down the drivers connected to it. the register map details the individual power-down settings for each output channel. these settings are found in 0x192[2], 0x195[2], 0x198[2], and 0x19b[2].
ad9520-5 rev. 0 | page 46 of 80 serial control port the ad9520 serial control port is a flexible, synchronous serial communications port that allows an easy interface with many industry-standard microcontrollers and microprocessors. the ad9520 serial control port is compatible with most synchronous transfer formats, including philips i2c, motorola? spi?, and intel? ssr protocols. the ad9520 i2c implementation deviates from the classic i2c specification on two specifications, and these deviations are documented in table 11 of this data sheet. the serial control port allows read/write access to all registers that configure the ad9520. spi/i2c port selection the ad9520 has two serial interfaces, spi and i2c. users can select either spi or i2c depending on the states of the three logic level (high, open, low) input pins, sp1 and sp0. when both sp1 and sp0 are high, the spi interface is active. otherwise, i2c is active with eight different i2c slave address (seven bits wide) settings, see table 35 . the four msbs of the slave address are hardware coded as 1011, and the three lsbs are programmed by sp1 and sp0. table 35. serial port mode selection sp1 sp0 address low low i2c, 1011000 low open i2c, 1011001 low high i2c, 1011010 open low i2c, 1011011 open open i2c, 1011100 open high i2c, 1011101 high low i2c, 1011110 high open i2c, 1011111 high high spi i2c serial port operation the ad9520 i2c port is based on the i2c fast mode standard. the ad9520 supports both i2c protocols: standard mode (100 khz) and fast mode (400 khz). the ad9520 i2c port has a 2-wire interface consisting of a serial data line (sda) and a serial clock line (scl). in an i2c bus system, the ad9520 is connected to the serial bus (data bus sda and clock bus scl) as a slave device, meaning that no clock is generated by the ad9520. the ad9520 uses direct 16-bit (two bytes) memory addressing instead of traditional 8-bit (one byte) memory addressing. i 2 c bus characteristics table 36. i 2 c bus definitions abbreviation definition s start sr repeated start p stop a acknowledge a no acknowledge w write r read one pulse on the scl clock line is generated for each data bit transferred. the data on the sda line must not change during the high period of the clock. the state of the data line can change only when the clock on the scl line is low. sda scl data line stable; data valid change of data allowed 0 7239-160 figure 43. valid bit transfer a start condition is a transition from high to low on the sda line while scl is high. the start condition is always generated by the master to initialize the data transfer. a stop condition is a transition from low to high on the sda line while scl is high. the stop condition is always generated by the master to end the data transfer. start condition s stop condition p sd a scl 07239-161 figure 44. start and stop conditions a byte on the sda line is always eight bits long. an acknowledge bit must follow every byte. bytes are sent msb first. the acknowledge bit is the ninth bit attached to any 8-bit data byte. an acknowledge bit is always generated by the receiving device (receiver) to inform the transmitter that the byte has been received. it is done by pulling the sda line low during the ninth clock pulse after each 8-bit data byte.
ad9520-5 rev. 0 | page 47 of 80 s d a msb acknowledge from slave-receiver acknowledge from slave-receiver scl s p 1 2 8 9 1 2 8 3 to 7 3 to 7 9 10 07239-162 figure 45. acknowledge bit s d a msb = 0 acknowledge from slave-receiver acknowledge from slave-receiver scl s p 1 2 8 9 1 2 8 3 to 7 3 to 7 9 10 07239-163 figure 46. data transfer process (master write mode, 2-byte transfer used for illustration) s d a acknowledge from master-receiver no acknowledge from slave-receiver scl s p 1 2 8 9 1 2 8 3 to 7 3 to 7 9 10 msb = 1 07239-164 figure 47. data transfer process (master read mode, 2-byte transfer used for illustration) the no acknowledge bit is the ninth bit attached to any 8-bit data byte. a no acknowledge bit is always generated by the receiving device (receiver) to inform the transmitter that the byte has not been received. it is done by leaving the sda line high during the ninth clock pulse after each 8-bit data byte. data transfer process the master initiates data transfer by asserting a start condition. this indicates that a data stream follows. all i2c slave devices connected to the serial bus respond to the start condition. the master then sends an 8-bit address byte over the sda line, consisting of a 7-bit slave address (msb first) plus an r/ w bit. this bit determines the direction of the data transfer, that is, whether data is written to or read from the slave device (0 = write, 1 = read). the peripheral whose address corresponds to the transmitted address responds by sending an acknowledge bit. all other devices on the bus remain idle while the selected device waits for data to be read from or written to it. if the r/ w bit is 0, the master (transmitter) writes to the slave device (receiver). if the r/ w bit is 1, the master (receiver) reads from the slave device (transmitter). the format for these commands is described in the data transfer format section. data is then sent over the serial bus in the format of nine clock pulses, one data byte (8-bit) from either master (write mode) or slave (read mode), followed by an acknowledge bit from the receiving device. the number of bytes that can be transmitted per transfer is unrestricted. in write mode, the first two data bytes immediately after the slave address byte are the internal memory (control registers) address bytes with the high address byte first. this addressing scheme gives a memory address up to 2 16 ? 1 = 65,535. the data bytes after these two memory address bytes are register data written into the control registers. in read mode, the data bytes after the slave address byte are register data read from the control registers. when all data bytes are read or written, stop conditions are established. in write mode, the master (transmitter) asserts a stop condition to end data transfer during the (10th) clock pulse following the acknowledge bit for the last data byte from the slave device (receiver). in read mode, the master device (receiver) receives the last data byte from the slave device (transmitter) but does not pull it low during the ninth clock pulse. this is known as a no acknowledge bit. by receiving the no acknowledge bit, the slave device knows that the data transfer is finished and releases the sda line. the master then takes the data line low during the low period before the 10th clock pulse and high during the 10th clock pulse to assert a stop condition. a repeated start (sr) condition can be used in place of a stop condition. furthermore, a start or stop condition can occur at any time, and partially transferred bytes are discarded.
ad9520-5 rev. 0 | page 48 of 80 data transfer format send byte formatthe send byte protocol is used to set up the register address for subsequent commands. s slave address w a ram address high byte a ram address low byte a p write byte formatthe write byte protocol is used to write a register address to the ram starting from the specified ram addres s. s slave address w a ram address high byte a ram address low byte a ram data 0 a ram data 1 a ram data 2 a p receive byte formatthe receive byte protocol is used to read the data byte(s) from ram starting from the current address. s slave address r a ram data 0 a ram data 1 a ram data 2 a p read byte formatthe combined format of the send byte and the receive byte. s slave address w a ram address high byte a ram address low byte a sr slave address r a ram data 0 a ram data 1 a ram data 2 a p i2c serial port timing sda scl s sr p s t fall t set; dat t low t rise t hld; str t hld; dat t high t fall t set; str t hld; str t spike t set; stp t rise t idle 07239-165 figure 48. i2c serial port timing table 37. ic timing definitions parameter description f i2c i2c clock frequency t idle bus idle time between stop and start conditions t hld; str hold time for repeated start condition t set; str setup time for repeated start condition t set; stp setup time for stop condition t hld; dat hold time for data t set; dat setup time for data t low duration of scl clock low t high duration of scl clock high t rise scl/sda rise time t fall scl/sda fall time t spike voltage spike pulse width that must be suppressed by the input filter
ad9520-5 rev. 0 | page 49 of 80 spi serial port operation pin descriptions sclk (serial clock) is the serial shift clock. this pin is an input. sclk is used to synchronize serial control port reads and writes. write data bits are registered on the rising edge of this clock, and read data bits are registered on the falling edge. this pin is internally pulled down by a 30 k resistor to ground. sdio (serial data input/output) is a dual-purpose pin and acts either as an input only (unidirectional mode) or as an input/ output (bidirectional mode). the ad9520 defaults to the bidirectional i/o mode (0x000[7] = 0b). sdo (serial data out) is used only in the unidirectional i/o mode (0x000[7]) as a separate output pin for reading back data. cs (chip select bar) is an active low control that gates the read and write cycles. when cs is high, sdo and sdio are in a high impedance state. this pin is internally pulled up by a 30 k resistor to vs. ad9520 serial control port sclk/scl 16 sdo 18 sdio/sda 17 cs 15 07239-036 figure 49. serial control port spi mode operation in spi mode, single or multiple byte transfers are supported, as well as msb first or lsb first transfer formats. the ad9520 serial control port can be configured for a single bidirectional i/o pin (sdio only) or for two unidirectional i/o pins (sdio/ sdo). by default, the ad9520 is in bidirectional mode. short instruction mode (8-bit instruction) is not supported. only long (16-bit) instruction mode is supported. a write or a read operation to the ad9520 is initiated by pulling cs low. the cs stalled high mode is supported in data transfers where three or fewer bytes of data (plus instruction data) are transferred (see ). in this mode, the table 38 cs pin can temporarily return high on any byte boundary, allowing time for the system controller to process the next byte. cs can go high on byte boundaries only and can go high during either part (instruction or data) of the transfer. during this period, the serial control port state machine enters a wait state until all data is sent. if the system controller decides to abort the transfer before all of the data is sent, the state machine must be reset by either completing the remaining transfers or by returning cs low for at least one complete sclk cycle (but fewer than eight sclk cycles). raising the cs pin on a nonbyte boundary terminates the serial transfer and flushes the buffer. in the streaming mode (see table 38 ), any number of data bytes can be transferred in a continuous stream. the register address is automatically incremented or decremented (see the spi msb/lsb first transfers section). cs must be raised at the end of the last byte to be transferred, thereby ending streaming mode. communication cycleinstruction plus data there are two parts to a communication cycle with the ad9520. the first part writes a 16-bit instruction word into the ad9520, coincident with the first 16 sclk rising edges. the instruction word provides the ad9520 serial control port with information regarding the data transfer, which is the second part of the communication cycle. the instruction word defines whether the upcoming data transfer is a read or a write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer. write if the instruction word is for a write operation, the second part is the transfer of data into the serial control port buffer of the ad9520. data bits are registered on the rising edge of sclk. the length of the transfer (one, two, or three bytes or streaming mode) is indicated by two bits (w1:w0) in the instruction byte. when the transfer is one, two, or three bytes, but not streaming, cs can be raised after each sequence of eight bits to stall the bus (except after the last byte, where it ends the cycle). when the bus is stalled, the serial transfer resumes when cs is lowered. raising the cs pin on a nonbyte boundary resets the serial control port. during a write, streaming mode does not skip over reserved or blank registers, and the user can write 0x00 to the reserved register addresses. because data is written into a serial control port buffer area, not directly into the actual control registers of the ad9520, an additional operation is needed to transfer the serial control port buffer contents to the actual control registers of the ad9520, thereby causing them to become active. the update registers operation consists of setting 0x232[0] = 1b (this bit is self- clearing). any number of bytes of data can be changed before executing an update registers. the update registers simultaneously actuates all register changes that have been written to the buffer since any previous update. read the ad9520 supports only the long instruction mode. if the instruction word is for a read operation, the next n 8 sclk cycles clock out the data from the address specified in the instruction word, where n is 1 to 3 as determined by w1:w0. if n = 4, the read operation is in streaming mode, continuing until cs is raised. streaming mode does not skip over reserved or blank registers. the readback data is valid on the falling edge of sclk.
ad9520-5 rev. 0 | page 50 of 80 spi msb/lsb first transfers the default mode of the ad9520 serial control port is the bidirectional mode. in bidirectional mode, both the sent data and the readback data appear on the sdio pin. it is also possible to set the ad9520 to unidirectional mode (0x000[7] = 1 and 0x000[0] = 1). in unidirectional mode, the readback data appears on the sdo pin. the ad9520 instruction word and byte data can be msb first or lsb first. any data written to 0x000 must be mirrored; the upper four bits ([7:4]) must mirror the lower four bits ([3:0]). this makes it irrelevant whether lsb first or msb first is in effect. as an example of this mirroring, see the default setting for 0x000, which mirrors bit 4 and bit 3. this sets the long instruction mode, which is the default and the only mode supported. a readback request reads the data that is in the serial control port buffer area or the data that is in the active registers (see figure 50 ). readback of the buffer or active registers is controlled by 0x004[0]. the ad9520 uses register address 0x000 to register address 0xb03. the default for the ad9520 is msb first. serial control port buffer registers update registers write register 0x232 = 0x001 to update registers active registers sclk/scl sdo sdio/sda cs 07239-037 when lsb first is set by 0x000[1] and 0x000[6], it takes effect immediately because it only affects the operation of the serial control port and does not require that an update be executed. when msb first mode is active, the instruction and data bytes must be written from msb to lsb. multibyte data transfers in msb first format start with an instruction byte that includes the register address of the most significant data byte. subsequent data bytes must follow in order from the high address to the low address. in msb first mode, the serial control port internal address generator decrements for each data byte of the multibyte transfer cycle. figure 50. relationship between seri al control port buffer registers and active registers of the ad9520 spi instruction word (16 bits) the msb of the instruction word is r/ w , which indicates whether the instruction is a read or a write. the next two bits (w1:w0) indicate the length of the transfer in bytes. the final 13 bits are the address (a12:a0) at which to begin the read or write operation. when lsb first is active, the instruction and data bytes must be written from lsb to msb. multibyte data transfers in lsb first format start with an instruction byte that includes the register address of the least significant data byte followed by multiple data bytes. in a multibyte transfer cycle, the internal byte address generator of the serial port increments for each byte. for a write, the instruction word is followed by the number of bytes of data indicated by bits[w1:w0], see table 38 . table 38. byte transfer count w1 the ad9520 serial control port register address decrements from the register address just written toward 0x000 for multibyte i/o operations if the msb first mode is active (default). if the lsb first mode is active, the register address of the serial control port increments from the address just written toward 0x232 for multibyte i/o operations. w0 bytes to transfer 0 0 1 0 1 2 1 0 3 1 streaming mode always terminates when it reaches 0x232. note that unused addresses are not skipped during multibyte i/o operations. table 39. streaming mode (no addresses are skipped) write mode 1 streaming mode bits[a12:a0] select the address within the register map that is written to or read from during the data transfer portion of the communications cycle. only bits[a9:a0] are needed to cover the range of the 0x232 registers used by the ad9520. bits[a12:a10] must always be 0b. for multibyte transfers, this address is the starting byte address. in msb first mode, subsequent bytes increment the address. address direction stop sequence lsb first increment 0x230, 0x231, 0x232, stop msb first decrement 0x001, 0x000, 0x232, stop
ad9520-5 rev. 0 | page 51 of 80 table 40. serial control port, 16-bit instruction word, msb first msb lsb i15 i14 i13 i12 i11 i10 i9 i8 i7 i6 i5 i4 i3 i2 i1 i0 r/ w w1 w0 a12 = 0 a11 = 0 a10 = 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 cs sclk don't care sdio a12 w0 w1 r/w a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 don't care don't care don't care 16-bit instruction header register (n) data register (n ? 1) data 0 7239-038 figure 51. serial control port writemsb firs t, 16-bit instruction, two bytes of data cs sclk sdio sdo register (n) data 16-bit instruction header register (n ? 1) data register (n ? 2) data register (n ? 3) data a12 w0w1 r/w a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 don't care don't care don't care don't care d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 07239-039 figure 52. serial control port readmsb firs t, 16-bit instruction, four bytes of data t s don't care don't care w1w0a12a11a10a9a8a7a6a5d4d3d2d1d0 don't care don't care r/w t ds t dh t high t low t clk t c cs sclk sdio 07239-040 figure 53. serial control port writemsb firs t, 16-bit instruction, timing measurements data bit n ? 1 data bit n cs sclk sdio sdo t dv 07239-041 figure 54. timing diagram for serial control port register read cs sclk don't care don't care 16-bit instruction header register (n) data register (n + 1) data sdio don't care don't care a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 d1d0r/w w1 w0 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 0 7239-042 figure 55. serial control port writelsb firs t, 16-bit instruction, two bytes of data
ad9520-5 rev. 0 | page 52 of 80 cs sclk sdio t high t low t clk t s t ds t dh t c bit n bit n + 1 0 7239-043 figure 56. serial control port timingwrite table 41. serial control port timing parameter description t ds setup time between data and rising edge of sclk t dh hold time between data and rising edge of sclk t clk period of the clock setup time between the cs falling edge and sclk rising edge (start of communication cycle) t s setup time between sclk rising edge and the cs rising edge (end of communication cycle) t c t high minimum period that sclk should be in a logic high state t low minimum period that sclk should be in a logic low state t dv sclk to valid sdio and sdo (see figure 54 )
ad9520-5 rev. 0 | page 53 of 80 eeprom operations the ad9520 contains an internal eeprom (nonvolatile memory). the eeprom can be programmed by users to create and store a user-defined register setting file when the power is off. this setting file can be used for power-up and chip reset as a default setting. the eeprom size is 512 bytes. during the data transfer process, the write and read registers via the serial port are generally not available except for one readback register, status_eeprom. to determine the data transfer state through the serial port in spi mode, users can read the value of status_eeprom (1 = in process and 0 = completed). in i2c mode, the user can address the ad9520 slave port with the external i2c master (send an address byte to the ad9520). if the ad9520 responds with a no acknowledge bit, the data transfer process is not done. if the ad9520 responds with an acknowledge bit, the data transfer process is completed. the user can monitor the status_eeprom register or program the status pin to monitor the status of the data transfer. writing to the eeprom the eeprom cannot be programmed directly through the serial port interface. to program the eeprom and store a register setting file, do the following: 1. program the ad9520 registers to the desired circuit state. 2. program the eeprom buffer registers, if necessary (see the programming the eeprom buffer segment section). t his is only necessary if users want to use the eeprom to control the default setting of some (but not all) of the ad9520 registers, or if they want to control the register setting update sequence during power-up or chip reset. 3. set the enable eeprom write bit (0xb02[0]) to 1 to enable the eeprom. 4. set the reg2eeprom bit (0xb03[0]) to 1. 5. set the io_update bit (0x232[0]) to 1, which starts the process of writing data into the eeprom to create the eeprom setting file. this enables the ad9520 eeprom controller to transfer the current register values, as well as the memory address and instru ction bytes from the eeprom buffer segment, into the eeprom. after the write process is completed, the internal controller sets 0xb03[0] (reg2eeprom) back to 0. the readback register status_eeprom (0xb00[0]) is used to indicate the data transfer status between the eeprom and the control registers (0 = done/inactive; 1 = in process/ active). at the beginning of the data transfer, status_eeprom is set to 1 by the eeprom controller and cleared to 0 at the end of the data transfer. the user can access status_eeprom through the status pin when the status pin is programmed to monitor status_eeprom. alternatively, the user can monitor the status_eeprom bit. 6. after the data transfer process is done (0xb00[0] = 0), set the enable eeprom write register (0xb02[0]) to 0 to disable writing to the eeprom. to verify that the data transfer has completed correctly, the user can verify that 0xb01[0] = 0. a value of 1 in this register indicates a data transfer error. reading from the eeprom th e following reset-related events can start the process of restoring the settings stored in eeprom to control registers. when the eeprom pin is set high, do any of the following: 1. power-up the ad9520. 2. perform a hardware chip reset by pulling the reset pin low, and then releasing reset . 3. set the self-clearing soft reset bit (0x000[5]) to 1. when the eeprom pin is set low, set the self-clearing soft_eeprom bit (0xb02[1]) to 1. the ad9520 then starts to read the eeprom and loads the values into the ad9520. if the eeprom pin is low during reset or power-up, the eeprom is not active, and the ad9520 default values are loaded instead. to verify that the data transfer has completed correctly, the user can verify that 0xb01[0] = 0. a value of 1 in this register indicates a data transfer error. programming the eeprom buffer segment the eeprom buffer segment is a register space on the ad9520 that allows the user to specify which groups of registers are stored to the eeprom during eeprom programming. normally, this segment does not need to be programmed by the user. instead, the default power-up values for the eeprom buffer segment allow the user to store all of the ad9520 register values from register 0x000 to register 0x231 to the eeprom. for example, if users want to load only the output driver settings from the eeprom without disturbing the pll register settings currently stored in the ad9520, they can alter the eeprom buffer segment to include only the registers that apply to the output drivers and exclude the registers that apply to the pll configuration. there are two parts to the eeprom buffer segment: register section definition groups and operational codes. each register section definition group contains the starting address and number of bytes to be written to the eeprom.
ad9520-5 rev. 0 | page 54 of 80 if the ad9520 register map were continuous from address 0x000 to address 0x232, only one register section definition group would consist of a starting address of 0x000 and a length of 563 bytes. however, this is not the case. the ad9520 register map is noncontiguous, and the eeprom is only 512 bytes long. therefore, the register section definition group tells the eeprom controller how the ad9520 register map is segmented. there are three operational codes: io_update, end-of-data, and pseudo-end-of-data. it is important that the eeprom buffer segment always have either an end-of-data or a pseudo-end-of-data operational code and that an io_update operation code appear at least once before the end-of-data op code. register section definition group the register section definition group is used to define a continuous register section for the eeprom profile. it consists of three bytes. the first byte defines how many continuous register bytes are in this group. if the user puts 0x000 in the first byte, it means there is only one byte in this group. if the user puts 0x001, it means there are two bytes in this group. the maximum number of registers in one group is 128. the next two bytes are the low byte and high byte of the memory address (16-bit) of the first register in this group. io_update (operational code 0x80) the eeprom controller uses this operational code to generate an io_update signal to update the active control register bank from the buffer register bank during the download process. at a minimum, there should be at least one io_update operational code after the end of the final register section definition group. this is needed is so that at least one io_update occurs after all of the ad9520 registers are loaded when the eeprom is read. if this operational code is absent during a write to the eeprom, the register values loaded from the eeprom are not transferred to the active register space, and these values do not take effect after they are loaded from the eeprom to the ad9520. end-of-data (operational code 0xff) the eeprom controller uses this operational code to terminate the data transfer process between eeprom and the control register during the upload and download process. the last item appearing in the eeprom buffer segment should be either this operational code or the pseudo-end-of-data operational code. pseudo-end-of-data (operational code 0xfe) the ad9520 eeprom buffer segment has 23 bytes that can contain up to seven register section definition groups. if users want to define more than seven register section definition groups, the pseudo-end-of-data operational code can be used. during the upload process, when the eeprom controller receives the pseudo-end-of-data operational code, it halts the data transfer process, clears the reg2eeprom bit, and enables the ad9520 serial port. users can then program the eeprom buffer segment again and reinitiate the data transfer process by setting the reg2eeprom bit (0xb03) to 1 and the io_update register (0x232) to 1. the internal i2c master then begins writing to the eeprom starting from the eeprom address held from the last writing. this sequence enables more discrete instructions to be written to the eeprom than would otherwise be possible due to the limited size of the eeprom buffer segment. it also permits the user to write to the same register multiple times with a different value each time. table 42. example of eeprom buffer segment reg addr (hex) bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) start eeprom buffer segment 0xa00 0 number of bytes [6:0] of the first group of registers 0xa01 address [15:8] of the first group of registers 0xa02 address [7:0] of the first group of registers 0xa03 0 number of bytes [6:0] of the second group of registers 0xa04 address [15:8] of the second group of registers 0xa05 address [7:0] of the second group of registers 0xa06 0 number of bytes [6:0] of the third group of registers 0xa07 address [15:8] of the third group of registers 0xa08 address [7:0] of the third group of registers 0xa09 io_update operational code (0x80) 0xa0a end-of-data operational code (0xff)
ad9520-5 rev. 0 | page 55 of 80 thermal performance table 43. thermal parameters for 64-lead lfcsp symbol thermal characteristic using a jedec jesd51-7 plus jedec jesd51-5 2s2p test board value (c/w) ja junction-to-ambient thermal resistance, 0.0 m/sec airflow per jedec jesd51-2 (still air) 22.0 jma junction-to-ambient thermal resistance, 1.0 m/sec airflow per jedec jesd51-6 (moving air) 19.2 jma junction-to-ambient thermal resistance, 2.0 m/sec airflow per jedec jesd51-6 (moving air) 17.2 jb junction-to-board characterization parameter, 1.0 m/sec airflow per jedec jesd51-6 (moving air) and jedec jesd51-8 11.6 jc junction-to-case thermal resistance (die-to -heat sink) per mil-std 883, method 1012.1 1.3 jt junction-to-top-of-package characterization paramete r, 0 m/sec airflow per jedec jesd51-2 (still air) 0.1 the ad9520 is specified for a case temperature (t case ). to ensure that t case is not exceeded, an airflow source can be used. use the following equation to determine the junction temperature on the application pcb: t j = t case + ( jt pd ) where: t j is the junction temperature (c). t case is the case temperature (c) measured by the user at the top center of the package. jt is the value from table 43 . pd is the power dissipation (see the total power dissipation in table 15 .) va lu e s of ja are provided for package comparison and pcb design considerations. ja can be used for a first-order approximation of t j by the equation t j = t a + ( ja pd ) where t a is the ambient temperature (c). va lu e s of jc are provided for package comparison and pcb design considerations when an external heat sink is required. va lu e s of jb are provided for package comparison and pcb design considerations.
ad9520-5 rev. 0 | page 56 of 80 register map register addresses that are not listed in table 44 are not used, and writing to those registers has no effect. the user should avoid writing values other than 00h to register addresses marked unused. table 44. register map overview addr (hex) parameter bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) serial port configuration 000 serial port config (spi mode) sdo active lsb first/ addr incr soft reset (self- clearing) unused unused soft reset (self- clearing) lsb first/ addr incr sdo active 00 serial port config (i2c mode) unused soft reset (self- clearing) unused unused soft reset (self- clearing) unused 00 001 unused n/a 002 reserved (read-only) n/a 003 reserved (read-only) n/a 004 readback control unused readback active regs 00 eeprom id 005 eeprom customer version id eeprom customer version id (lsb) 00 006 eeprom customer version id (msb) 00 007 to 00f unused 00 pll 010 pfd charge pump pfd polarity charge pump current charge pump mode pll power-down 7d 011 r counter 14-bit r counter, bits[7:0] (lsb) 01 012 unused 14-bit r counter, bits[13:8] (msb) 00 013 a counter unused 6-bit a counter 00 014 b counter 13-bit b counter, bits[7:0] (lsb) 03 015 unused 13-bit b counter, bits[12:8] (msb) 00 016 pll_ctrl_1 set cp pin to vcp/2 reset r counter reset a and b counters reset all counters b counter bypass prescaler p 06 017 pll_ctrl_2 status pin control antibacklash pulse width 00 018 pll_ctrl_3 enable cmos reference input dc offset lock detect counter digital lock detect window disable digital lock detect unused 06 019 pll_ctrl_4 r, a, b counters sync pin reset r path delay n path delay 00 01a pll_ctrl_5 enable status pin divider ref freq monitor threshold ld pin control 00 01b pll_ctrl_6 enable clk frequency monitor enable ref2 ( refin ) frequency monitor enable ref1 (refin) frequency monitor refmon pin control 00 01c pll_ctrl_7 disable switchover deglitch select ref2 use ref_sel pin enable automatic reference switchover stay on ref2 enable ref2 enable ref1 enable differential reference 00 01d pll_ctrl_8 enable status_eeprom at status pin enable xtal osc enable clock doubler disable pll status register enable ld pin comparator unused enable external holdover enable holdover 80
ad9520-5 rev. 0 | page 57 of 80 addr (hex) parameter bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) 01e pll_ctrl_9 unused enable zero delay unused 00 01f pll_readback (read-only) unused holdover active ref2 selected clk freq > threshold ref2 freq > threshold ref1 freq > threshold digital lock detect n/a output driver control 0f0 out0 control out0 format out0 cmos configuration out0 polarity out0 lvpecl differential voltage out0 lvpecl power-down 64 0f1 out1 control out1 format out1 cmos configuration out1 polarity out1 lvpecl differential voltage out1 lvpecl power-down 64 0f2 out2 control out2 format out2 cmos configuration out2 polarity out2 lvpecl differential voltage out2 lvpecl power-down 64 0f3 out3 control out3 format out3 cmos configuration out3 polarity out3 lvpecl differential voltage out3 lvpecl power-down 64 0f4 out4 control out4 format out4 cmos configuration out4 polarity out4 lvpecl differential voltage out4 lvpecl power-down 64 0f5 out5 control out5 format out5 cmos configuration out5 polarity out5 lvpecl differential voltage out5 lvpecl power-down 64 0f6 out6 control out6 format out6 cmos configuration out6 polarity out6 lvpecl differential voltage out6 lvpecl power-down 64 0f7 out7 control out7 format out7 cmos configuration out7 polarity out7 lvpecl differential voltage out7 lvpecl power-down 64 0f8 out8 control out8 format out8 cmos configuration out8 polarity out8 lvpecl differential voltage out8 lvpecl power-down 64 0f9 out9 control out9 format out9 cmos configuration out9 polarity out9 lvpecl differential voltage out9 lvpecl power-down 64 0fa out10 control out10 format out10 cmos configuration out10 polarity out10 lvpecl differential voltage out10 lvpecl power-down 64 0fb out11 control out11 format out11 cmos configuration out11 polarity out11 lvpecl differential voltage out11 lvpecl power-down 64 0fc enable output on csdld csdld en out7 csdld en out6 csdld en out5 csdld en out4 csdld en out3 csdld en out2 csdld en out1 csdld en out0 00 0fd enable output on csdld unused csdld en out11 csdld en out10 csdld en out9 csdld en out8 00 0fe to 18f unused 00 lvpecl channel dividers 190 divider 0 (pecl) divider 0 low cycles divider 0 high cycles 77 191 divider 0 bypass divider 0 ignore sync divider 0 force high divider 0 start high divider 0 phase offset 00 192 unused channel 0 power- down channel 0 direct-to- output disable divider 0 dcc 00
ad9520-5 rev. 0 | page 58 of 80 addr (hex) parameter bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) 193 divider 1 (pecl) divider 1 low cycles divider 1 high cycles 33 194 divider 1 bypass divider 1 ignore sync divider 1 force high divider 1 start high divider 1 phase offset 00 195 unused unused channel 1 power- down channel 1 direct-to- output disable divider 1 dcc 00 196 divider 2 (pecl) divider 2 low cycles divider 2 high cycles 11 197 divider 2 bypass divider 2 ignore sync divider 2 force high divider 2 start high divider 2 phase offset 00 198 unused unused channel 2 power- down channel 2 direct-to- output disable divider 2 dcc 00 199 divider 3 (pecl) divider 3 low cycles divider 3 high cycles 00 19a divider 3 bypass divider 3 ignore sync divider 3 force high divider 3 start high divider 3 phase offset 00 19b unused unused channel 3 power- down channel 3 direct-to- output disable divider 3 dcc 00 19c to 1df unused 00 vco divider and clk input 1e0 vco divider unused unused vco divider 00 1e1 input clks unused unused (default = 01b) power - down clock input section reserved bypass vco divider 20 1e2 to 22a unused 00 system 230 power-down and sync unused disable power-on sync power- down sync power- down distribution reference soft sync 00 231 unused unused 00 update all registers 232 io_update unus ed io_update (self-clearing) 00 233 to 9ff unused 00 eeprom buffer segment a00 eeprom buffer segment register 1 0 eeprom buffer segment register 1 (default: number of bytes for group 1) 00 a01 eeprom buffer segment register 2 eeprom buffer segment register 2 (default: bits[15:8] of starting register address for group 1) 00 a02 eeprom buffer segment register 3 eeprom buffer segment register 3 (default: bits[7:0 ] of starting register address for group 1) 00 a03 eeprom buffer segment register 4 0 eeprom buffer segment register 4 (default: number of bytes for group 2) 02
ad9520-5 rev. 0 | page 59 of 80 addr (hex) parameter bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) a04 eeprom buffer segment register 5 eeprom buffer segment register 5 (default: bits[15:8] of starting register address for group 2) 00 a05 eeprom buffer segment register 6 eeprom buffer segment register 6 (default: bits[7:0 ] of starting register address for group 2) 04 a06 eeprom buffer segment register 7 0 eeprom buffer segment register 7 (default: number of bytes for group 3) 0e a07 eeprom buffer segment register 8 eeprom buffer segment register 8 (default: bits[15:8] of starting register address for group 3) 00 a08 eeprom buffer segment register 9 eeprom buffer segment register 9 (default: bits[7:0 ] of starting register address for group 3) 10 a09 eeprom buffer segment register 10 0 eeprom buffer segment register 10 (default: number of bytes for group 4) 0e a0a eeprom buffer segment register 11 eeprom buffer segment register 11 (default: bits[15:8] of starting register address for group 4) 00 a0b eeprom buffer segment register 12 eeprom buffer segment register 12 (d efault: bits[7:0] of starting register address for group 4) f0 a0c eeprom buffer segment register 13 0 eeprom buffer segment register 13 (default: number of bytes for group 5) 0b a0d eeprom buffer segment register 14 eeprom buffer segment register 14 (default: bits[15:8] of starting register address for group 5) 01 a0e eeprom buffer segment register 15 eeprom buffer segment register 15 (d efault: bits[7:0] of starting register address for group 5) 90 a0f eeprom buffer segment register 16 0 eeprom buffer segment register 16 (default: number of bytes for group 6) 01 a10 eeprom buffer segment register 17 eeprom buffer segment register 17 (default: bits[15:8] of starting register address for group 6) 01 a11 eeprom buffer segment register 18 eeprom buffer segment register 18 (d efault: bits[7:0] of starting register address for group 6) e0 a12 eeprom buffer segment register 19 0 eeprom buffer segment register 19 (default: number of bytes for group 7) 01 a13 eeprom buffer segment register 20 eeprom buffer segment register 20 (default: bits[15:8] of starting register address for group 7) 02
ad9520-5 rev. 0 | page 60 of 80 addr (hex) parameter bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) a14 eeprom buffer segment register 21 eeprom buffer segment register 21 (d efault: bits[7:0] of starting register address for group 7) 30 a15 eeprom buffer segment register 22 eeprom buffer segment register 22 (default: io_update from eeprom) 80 a16 eeprom buffer segment register 23 eeprom buffer segment register 23 (default: end of data) ff a17 to aff unused 00 eeprom control b00 eeprom status (read-only) unused unused status_ eeprom 00 b01 eeprom error checking (read-only) unused unused eeprom data error 00 b02 eeprom control 1 unused soft_eeprom (self-clearing) enable eeprom write 00 b03 eeprom control 2 unused unused reg2eeprom (self-clearing) 00
ad9520-5 rev. 0 | page 61 of 80 register map descriptions table 45 through table 55 provide a detailed description of each of the control register functions. the registers are listed by hexadecimal address. reference to a specific bit or range of bits within a register is indicated by squared brackets. for example, [3] refe rs to bit 3 and [5:2] refers to the range of bits from bit 5 through bit 2. table 45. spi mode serial port configuration reg addr (hex) bit(s) name description 000 [7] sdo active selects unidirectional or bidirectional data transfer mode. [7] = 0; sdio pin used for write and read; sdo is high impedance (default). [7] = 1; sdo used for read; sdio used for write; unidirectional mode. 000 [6] lsb first/addr incr spi msb or lsb data orientation. (this register is ignored in i 2 c mode.) [6] = 0; data-oriented msb first; addressing decrements (default). [6] = 1; data-oriented lsb first; addressing increments. 000 [5] soft reset soft reset. [5] = 1 (self-clearing). soft reset; restor es default values to internal registers. 000 [4] unused 000 [3:0] mirror[7:4] bits[3:0] should always mirror bits[7:4] so th at it does not matter whether the part is in msb or lsb first mode (see regi ster 0x000[6]). set bits as follows: [0] = [7] [1] = [6] [2] = [5] [3] = [4] 004 [0] readback active registers select register bank used for a readback. [0] = 0; read back buffer registers (default). [0] = 1; read back active registers. table 46. i 2 c mode serial port configuration reg addr (hex) bit(s) name description 000 [7:6] unused 000 [5] soft reset soft reset. [5] = 1 (self-clearing). soft reset; rest ores default values to internal registers. 000 [4] unused 000 [3:0] mirror[7:4] bits[3:0] should always mirror bits[7:4] so th at it does not matter whether the part is in msb or lsb first mode (see regist er 0x000[6]). set bits as follows: [0] = [7] [1] = [6] [2] = [5] [3] = [4] 004 [0] readback active registers select register bank used for a readback. [0] = 0; read back buffer registers (default). [0] = 1; read back active registers. table 47. eeprom id reg addr (hex) bit(s) name description 005 [7:0] eeprom customer version id (lsb) 16-bit eeprom id[7:0]. this register, along with 0x006, allows the user to store a unique id to identify which version of th e ad9520 register settings is stored in the eeprom. it does not affect ad9520 ope ration in any way (default: 0x00). 006 [7:0] eeprom customer version id (msb) 16-bit eeprom id[15:8]. this register, along with 0x005, allows the user to store a unique id to identify which version of th e ad9520 register settings is stored in the eeprom. it does not affect ad9520 ope ration in any way (default: 0x00).
ad9520-5 rev. 0 | page 62 of 80 table 48. pll reg. addr (hex) bit(s) name description 010 [7] pfd polarity sets the pfd polarity. negative polari ty is for use (if needed) with external vco/vcxo. [7] = 0; positive (higher control voltag e produces higher frequency) (default). [7] = 1; negative (higher control voltage produces lower frequency). 010 [6:4] cp current charge pump current (with cprset = 5.1 k). [6] [5] [4] i cp (ma) 0 0 0 0.6 0 0 1 1.2 0 1 0 1.8 0 1 1 2.4 1 0 0 3.0 1 0 1 3.6 1 1 0 4.2 1 1 1 4.8 (default) 010 [3:2] cp mode charge pump operating mode. [3] [2] charge pump mode 0 0 high impedance state. 0 1 force source current (pump-up). 1 0 force sink current (pump-down). 1 1 normal operation (default). 010 [1:0] pll power- down pll operating mode. [1] [0] mode 0 0 normal operation; this mode must be selected to use the pll. 0 1 asynchronous power-down (default). 1 0 unused. 1 1 synchronous power-down. 011 [7:0] 14-bit r counter, bits[7:0] (lsb) reference divider lsbslower eight bits. the reference divider (also called the r divider or r counter) is 14 bits long. the lower eight bits are in this register (default: 0x01). 012 [5:0] 14-bit r counter, bits[13:8] (msb) reference divider msbsupper six bits. the reference di vider (also called the r divider or r counter) is 14 bits long. the upper six bits are in this register (default: 0x00). 013 [5:0] 6-bit a counter a counter (part of n divider). the n di vider is also called the feed back divider (default: 0x00). 014 [7:0] 13-bit b counter, bits[7:0] (lsb) b counter (part of n divider)lower eight bits. the n divi der is also called the feed back divider (default: 0x03). 015 [4:0] 13-bit b counter, bits[12:8] (msb) b counter (part of n divider)upper five bits. the n divi der is also called the feed back divider (default: 0x00). 016 [7] set cp pin to vcp/2 sets the cp pin to one-half of the vcp supply voltage. [7] = 0; cp normal operation (default). [7] = 1; cp pin set to vcp/2. 016 [6] reset r counter reset r counter (r divider). [6] = 0; normal (default). [6] = 1; hold r counter in reset. 016 [5] reset a and b counters reset a and b counters (part of n divider). [5] = 0; normal (default). [5] = 1; hold a and b counters in reset. 016 [4] reset all counters reset r, a, and b counters. [4] = 0; normal (default). [4] = 1; hold r, a, and b counters in reset.
ad9520-5 rev. 0 | page 63 of 80 reg. addr (hex) bit(s) name description 016 [3] b counter bypass b counter bypass. this is only valid when operating the prescaler in fd mode. [3] = 0; normal (default). [3] = 1; b counter is set to divide-by-1. this allows the prescaler setting to determine the divide for the n divider. 016 [2:0] prescaler p prescaler: dm = dual modulus and fd = fixe d divide. the prescaler p is part of the feedback divider. [2] [1] [0] mode prescaler 0 0 0 fd divide-by-1. 0 0 1 fd divide-by-2. 0 1 0 dm divide-by-2 and divide-by-3 when a 0; divide-by-2 when a = 0. 0 1 1 dm divide-by-4 and divide-by-5 when a 0; divide-by-4 when a = 0. 1 0 0 dm divide-by-8 and divide-by-9 when a 0; divide-by-8 when a = 0. 1 0 1 dm divide-by-16 and divide-by-17 when a 0; divide-by-16 when a = 0. 1 1 0 dm divide-by-32 and divide-by-33 wh en a 0; divide-by-32 when a = 0 (default). 1 1 1 fd divide-by-3. 017 [7:2] status pin control selects the signal that appears at the status pin. 0x01d[7] must be 0 to reprogram the status pin. [7] [6] [5] [4] [3] [2] level or dynamic signal signal at status pin 0 0 0 0 0 0 lvl ground, dc (default). 0 0 0 0 0 1 dyn n divider output (after the delay). 0 0 0 0 1 0 dyn r divider output (after the delay). 0 0 0 0 1 1 dyn a divider output. 0 0 0 1 0 0 dyn prescaler output. 0 0 0 1 0 1 dyn pfd up pulse. 0 0 0 1 1 0 dyn pfd down pulse. 0 x x x x x lvl ground (dc); for all other cases of 0xxxxx not specified. the selections that follow are the same as for refmon. 1 0 0 0 0 0 lvl ground (dc). 1 0 0 0 0 1 dyn ref1 clock (differential reference when in differential mode). 1 0 0 0 1 0 dyn ref2 clock (n/a in differential mode). 1 0 0 0 1 1 dyn selected reference to pll (differential reference when in differential mode). 1 0 0 1 0 0 dyn unselected reference to pll (not available in differential mode). 1 0 0 1 0 1 lvl status of selected reference (status of differential reference); active high. 1 0 0 1 1 0 lvl status of unselected reference (not available in differential mode); active high. 1 0 0 1 1 1 lvl status ref1 frequency (active high). 1 0 1 0 0 0 lvl status ref2 frequency (active high). 1 0 1 0 0 1 lvl (status ref1 frequency) and (status ref2 frequency). 1 0 1 0 1 0 lvl (dld) and (status of selected reference) and (status of vco). 1 0 1 0 1 1 lvl status of clk frequency (active high). 1 0 1 1 0 0 lvl selected reference (low = ref1, high = ref2). 1 0 1 1 0 1 lvl dld; active high. 1 0 1 1 1 0 lvl holdover active (active high). 1 0 1 1 1 1 lvl ld pin comparator output (active high). 1 1 0 0 0 0 lvl vs (pll power supply). 1 1 0 0 0 1 dyn ref1 clock (differential reference when in differential mode). 1 1 0 0 1 0 dyn ref2 clock (not available in differential mode). 1 1 0 0 1 1 dyn selected reference to pll (differential reference when in differential mode).
ad9520-5 rev. 0 | page 64 of 80 reg. addr (hex) bit(s) name description [7] [6] [5] [4] [3] [2] level or dynamic signal signal at status pin 1 1 0 1 0 0 dyn unselected reference to pll (not available when in differential mode). 1 1 0 1 0 1 lvl status of selected reference (status of differential reference); active low. 1 1 0 1 1 0 lvl status of unselected reference (not available in differential mode); active low. 1 1 0 1 1 1 lvl status of ref1 frequency (active low). 1 1 1 0 0 0 lvl status of ref2 frequency (active low). 1 1 1 0 0 1 lvl (status of ref1 frequency) and (status of ref2 frequency) . 1 1 1 0 1 0 lvl (dld) and (status of selected reference) and (status of vco) . 1 1 1 0 1 1 lvl status of clk frequency (active low). 1 1 1 1 0 0 lvl selected reference (low = ref2, high = ref1). 1 1 1 1 0 1 lvl dld (active low). 1 1 1 1 1 0 lvl holdover active (active low). 1 1 1 1 1 1 lvl ld pin comparator output (active low). 017 [1:0] antibacklash pulse width [1] [0] antibacklash pulse width (ns) 0 0 2.9 (default) 0 1 1.3 1 0 6.0 1 1 2.9 018 [7] enable cmos reference input dc offset enables dc offset in single-ended cmos input mode to prevent chattering when ac-coupled and input is lost. [7] = 0; disable dc offset (default). [7] = 1; enable dc offset. 018 [6:5] lock detect counter required consecutive number of pfd cycles with edges inside lock detect window before the dld indicates a locked condition. [6] [5] pfd cycles to determine lock 0 0 5 (default) 0 1 16 1 0 64 1 1 255 018 [4] digital lock detect window if the time difference of the rising edges at the inputs to the pfd are less than the lock detect window time, the digital lock detect flag is set. the flag remains set until the time difference is greater than the loss-of-lock threshold. [4] = 0; high range (default). [4] = 1; low range. 018 [3] disable digital lock detect digital lock detect operation. [3] = 0; normal lock detect operation (default). [3] = 1; disable lock detect. 019 [7:6] r, a, b counters sync pin reset [7] [6] action 0 0 do nothing on sync (default). 0 1 asynchronous reset. 1 0 synchronous reset. 1 1 do nothing on sync . 019 [5:3] r path delay r path delay, see table 2 (default: 0x0). 019 [2:0] n path delay n path delay, see table 2 (default: 0x0).
ad9520-5 rev. 0 | page 65 of 80 reg. addr (hex) bit(s) name description 01a [7] enable status pin divider enables a divide-by-4 on the status pin. this makes it easier to look at low duty-cycle signals out of the r and n dividers. [7] = 0; divide-by-4 disabled on status pin (default). [7] = 1; divide-by-4 enabled on status pin. 01a [6] ref freq monitor threshold sets the reference (ref1/ref2) frequency monitors detect ion threshold frequency. this does not affect the clk frequency monitors detection threshold (see table 14 , ref1, ref2, and clk frequency status monitor parameter). [6] = 0; frequency valid if frequency is above 1.02 mhz (default). [6] = 1; frequency valid if frequency is above 6 khz. 01a [5:0] ld pin control selects the signal that is connected to the ld pin. [5] [4] [3] [2] [1] [0] level or dynamic signal signal at ld pin 0 0 0 0 0 0 lvl digital lock detect (high = lock; low = unlock, default). 0 0 0 0 0 1 dyn p-channel, open-drain lock detect (analog lock detect). 0 0 0 0 1 0 dyn n-channel, open-drain lock detect (analog lock detect). 0 0 0 0 1 1 hiz tristate (high-z) ld pin. 0 0 0 1 0 0 cur current source lock detect (110 a when dld is true). 0 x x x x x lvl ground (dc); for all other cases of 0xxxxx not specified. the selections that follow are the same as for refmon. 1 0 0 0 0 0 lvl ground (dc). 1 0 0 0 0 1 dyn ref1 clock (differential reference when in differential mode). 1 0 0 0 1 0 dyn ref2 clock (n/a in differential mode). 1 0 0 0 1 1 dyn selected reference to pll (differential reference when in differential mode). 1 0 0 1 0 0 dyn unselected reference to pll (not available in differential mode). 1 0 0 1 0 1 lvl status of selected reference (status of differential reference); active high. 1 0 0 1 1 0 lvl status of unselected reference (not available in differential mode); active high. 1 0 0 1 1 1 lvl status ref1 frequency (active high). 1 0 1 0 0 0 lvl status ref2 frequency (active high). 1 0 1 0 0 1 lvl (status ref1 frequency) and (status ref2 frequency). 1 0 1 0 1 0 lvl (dld) and (status of selected reference) and (status of vco). 1 0 1 0 1 1 lvl status of clk frequency (active high). 1 0 1 1 0 0 lvl selected reference (low = ref1, high = ref2). 1 0 1 1 0 1 lvl dld; active high. 1 0 1 1 1 0 lvl holdover active (active high). 1 0 1 1 1 1 lvl n/a, do not use. 1 1 0 0 0 0 lvl vs (pll supply). 1 1 0 0 0 1 dyn ref1 clock (differential reference when in differential mode). 1 1 0 0 1 0 dyn ref2 clock (not available in differential mode). 1 1 0 0 1 1 dyn selected reference to pll (differential reference when in differential mode). 1 1 0 1 0 0 dyn unselected reference to pll (not available when in differential mode). 1 1 0 1 0 1 lvl status of selected reference (status of differential reference); active low. 1 1 0 1 1 0 lvl status of unselected reference (not available in differential mode); active low. 1 1 0 1 1 1 lvl status of ref1 frequency (active low). 1 1 1 0 0 0 lvl status of ref2 frequency (active low). 1 1 1 0 0 1 lvl (status of ref1 frequency) and (status of ref2 frequency) .
ad9520-5 rev. 0 | page 66 of 80 reg. addr (hex) bit(s) name description [5] [4] [3] [2] [1] [0] level or dynamic signal signal at ld pin 1 1 1 0 1 0 lvl (dld) and (status of selected reference) and (status of vco) . 1 1 1 0 1 1 lvl status of clk frequency (active low). 1 1 1 1 0 0 lvl selected reference (low = ref2, high = ref1). 1 1 1 1 0 1 lvl dld; active low. 1 1 1 1 1 0 lvl holdover active (active low). 1 1 1 1 1 1 lvl n/a, do not use. 01b [7] enable clk frequency monitor enables or disables the external clk frequency monitor. [7] = 0; disable the external clk frequency monitor (default). [7] = 1; enable the external clk frequency monitor. 01b [6] enable ref2 ( refin ) frequency monitor enables or disables the ref2 frequency monitor. [6] = 0; disable the ref2 frequency monitor (default). [6] = 1; enable the ref2 frequency monitor. 01b [5] enable ref1 (refin) frequency monitor ref1 (refin) frequency monitor enabled; this is for both ref1 (single-ende d) and refin (differential) inputs (as selected by differential reference mode). [5] = 0; disable the ref1 (refin) frequency monitor (default). [5] = 1; enable the ref1 (refin) frequency monitor. 01b [4:0] refmon pin control selects the signal that is connected to the refmon pin. [4] [3] [2] [1] [0] level or dynamic signal signal at refmon pin 0 0 0 0 0 lvl ground, dc (default). 0 0 0 0 1 dyn ref1 clock (differential reference when in differential mode). 0 0 0 1 0 dyn ref2 clock (n/a in differential mode). 0 0 0 1 1 dyn selected reference to pll (differential reference when in differential mode). 0 0 1 0 0 dyn unselected reference to pll (not available in differential mode). 0 0 1 0 1 lvl status of selected reference (status of differential reference); active high. 0 0 1 1 0 lvl status of unselected reference (not available in differential mode); active high. 0 0 1 1 1 lvl status ref1 frequency (active high). 0 1 0 0 0 lvl status ref2 frequency (active high). 0 1 0 0 1 lvl (status ref1 frequency) and (status ref2 frequency). 0 1 0 1 0 lvl (dld) and (status of selected reference) and (status of vco). 0 1 0 1 1 lvl status of clk frequency (active high). 0 1 1 0 0 lvl selected reference (low = ref1, high = ref2). 0 1 1 0 1 lvl dld; active low. 0 1 1 1 0 lvl holdover active (active high). 0 1 1 1 1 lvl ld pin comparator output (active high). 1 0 0 0 0 lvl vs (pll supply). 1 0 0 0 1 dyn ref1 clock (differential reference when in differential mode). 1 0 0 1 0 dyn ref2 clock (not available in differential mode). 1 0 0 1 1 dyn selected reference to pll (differential reference when in differential mode). 1 0 1 0 0 dyn unselected reference to pll (not available when in differential mode).
ad9520-5 rev. 0 | page 67 of 80 reg. addr (hex) bit(s) name description [4] [3] [2] [1] [0] level or dynamic signal signal at refmon pin 1 0 1 0 1 lvl status of selected reference (status of differential reference); active low. 1 0 1 1 0 lvl status of unselected reference (not available in differential mode); active low. 1 0 1 1 1 lvl status of ref1 frequency (active low). 1 1 0 0 0 lvl status of ref2 frequency (active low). 1 1 0 0 1 lvl (status of ref1 frequency) and (status of ref2 frequency) . 1 1 0 1 0 lvl (dld) and (status of selected reference) and (status of vco) . 1 1 0 1 1 lvl status of clk frequency (active low). 1 1 1 0 0 lvl selected reference (low = ref2, high = ref1). 1 1 1 0 1 lvl dld; active low. 1 1 1 1 0 lvl holdover active (active low). 1 1 1 1 1 lvl ld pin comparator output (active low). 01c [7] disable switchover deglitch disables or enables the switchover deglitch circuit. [7] = 0; enable the switchover deglitch circuit (default). [7] = 1; disable the switchover deglitch circuit. 01c [6] select ref2 if register 0x01c[5] = 0, selects the reference for pll when in manual; register selected reference control . [6] = 0; select ref1 (default). [6] = 1; select ref2. 01c [5] use ref_sel pin if register 0x01c[4] = 0 (manual), sets the method of pll reference selection. [5] = 0; use register 0x01c[6] (default). [5] = 1; use ref_sel pin. 01c [4] enable automatic reference switchover automatic or manual reference switchover. single-ended reference mode must be selected by register 0x01c[0] = 0. [4] = 0; manual reference switchover (default). [4] = 1; automatic reference switchover. setting this bit also powers on ref1 and ref2 and overrides the settings in register 0x01c[2:1]. 01c [3] stay on ref2 stays on ref2 after switchover. [3] = 0; return to ref1 automatically when ref1 status is good again (default). [3] = 1; stay on ref2 after switchover. do not automatically return to ref1. 01c [2] enable ref2 this bit turns the ref2 power on. this bi t is overridden when automatic reference switchover is enabled. [2] = 0; ref2 power off (default). [2] = 1; ref2 power on. 01c [1] enable ref1 this bit turns the ref1 power on. this bi t is overridden when automatic reference switchover is enabled. [1] = 0; ref1 power off (default). [1] = 1; ref1 power on. 01c [0] enable differential reference selects the pll reference mode, differential or single-ended. register 0x01c[2:1] should be cleared when this bit is set. [0] = 0; single-ended reference mode (default). [0] = 1; differential reference mode. 01d [7] enable status_eeprom at status pin enables the status_eeprom signal at the status pin. [7] = 0; the status pin is controlled by the 0x017[7:2] selection. [7] = 1; select the status_eeprom signal at the status pin. this bit overrides 0x017[7:2] (default). 01d [6] enable xtal osc enables the maintaining amplifier needed by a crystal oscillator at the pll reference input. [6] = 0; crystal oscillator main taining amplifier disabled (default). [6] = 1; crystal oscillator maintaining amplifier enabled.
ad9520-5 rev. 0 | page 68 of 80 reg. addr (hex) bit(s) name description 01d [5] enable clock doubler enable pll reference input clock doubler. [5] = 0; doubler disabled (default). [5] = 1; doubler enabled. 01d [4] disable pll status register disables the pll status register readback. [4] = 0; pll status register enabled (default). [4] = 1; pll status register disabled. if this bi t is set, register 01f is not automatically updated. 01d [3] enable ld pin comparator enables the ld pin voltage comparator. this is used with the ld pin current source lock detect mode. when the ad9520 is in internal (automatic) holdover mode, this enables the use of the voltage on the ld pin to determine if the pll was previously in a locked state (see figure 34 ). otherwise, this can be used with the refmon and status pins to monitor the voltage on the ld pin. [3] = 0; disable ld pin comparator and ignore the ld pin voltage; internal/automatic holdover controller treats this pin as true (high, default). [3] = 1; enable ld pin comparator (use ld pin voltage to determine if the pll was previously locked). 01d [1] enable external holdover enables the external hold control through the sync pin. (this disables the internal holdover mode.) [1] = 0; automatic holdover mode, holdover co ntrolled by automatic holdover circuit (default). [1] = 1; external holdover mode, holdover controlled by sync pin. 01d [0] enable holdover enables the internally controlled holdover function. [0] = 0; holdover disabled (default). [0] = 1; holdover enabled. 01e [1] enable zero delay enables zero delay function. [1] = 0; disables zero delay function (default). [1] = 1; enables zero delay function. 01f [5] holdover active (read-only) readback register. indicates if the part is in the holdover state (see figure 34 ). this is not the same as holdover enabled. [5] = 0; not in holdover. [5] = 1; holdover state active. 01f [4] ref2 selected (read-only) readback register. indicates which pll referenc e is selected as the input to the pll. [4] = 0; ref1 selected (or differential reference if in differential mode). [4] = 1; ref2 selected. 01f [3] clk frequency > threshold (read-only) readback register. indicates if the external clk in put frequency is greater than the threshold (see table 14 , ref1, ref2, and external clk frequency status monitor parameter). [3] = 0; the external clk freq uency is less than the threshold. [3] = 1; the external clk freque ncy is greater than the threshold. 01f [2] ref2 frequency > threshold (read-only) readback register. indicates if the frequency of the sign al at ref2 is greater than the threshold frequency set by register 0x01a[6]. [2] = 0; ref2 frequency is less than the threshold frequency. [2] = 1; ref2 frequency is greater than the threshold frequency. 01f [1] ref1 frequency > threshold (read-only) readback register. indicates if the frequency of the sign al at ref1 is greater than the threshold frequency set by register 0x01a[6]. [1] = 0; ref1 frequency is less than the threshold frequency. [1] = 1; ref1 frequency is greater than the threshold frequency. 01f [0] digital lock detect (read-only) readback register. digital lock detect. [0] = 0; pll is not locked. [0] = 1; pll is locked.
ad9520-5 rev. 0 | page 69 of 80 table 49. output driver control reg. addr (hex) bit(s) name description 0f0 [7] out0 format selects the output type for out0. [7] = 0; lvpecl (default). [7] = 1; cmos. 0f0 [6:5] out0 cmos configuration sets the cmos output configuration for out0 when 0x0f0[7] = 1. [6:5] out0a out0b 00 tristate tristate 01 on tristate 10 tristate on 11 (default) on on 0f0 [4:3] out0 polarity sets the output polarity for out0. [7] [4] [3] output type out0a out0b 0 (default) x 0 (default) lvpecl noninverting inverting 0 x 1 lvpecl inverting noninverting 1 0 (default) 0 cmos noninverting noninverting 1 0 1 cmos inverting inverting 1 1 0 cmos noninverting inverting 1 1 1 cmos inverting noninverting 0f0 [2:1] out0 lvpecl differential voltage sets the lvpecl output differential voltage (v od ). [2] [1] v od (mv) 0 0 400 0 1 600 1 (default) 0 (default) 780 1 1 960 0f0 [0] out0 lvpecl power-down lvpecl power-down. [0] = 0; normal operation (default). [0] = 1; safe power-down. 0f1 [7:0] out1 control this register controls out1, and the bit assignments for this register are identical to register 0x0f0. 0f2 [7:0] out2 control this register controls out2, and the bit assignments for this register are identical to register 0x0f0. 0f3 [7:0] out3 control this register controls out3, and the bit assignments for this register are identical to register 0x0f0. 0f4 [7:0] out4 control this register controls out4, and the bit assignments for this register are identical to register 0x0f0. 0f5 [7:0] out5 control this register controls out5, and the bit assignments for this register are identical to register 0x0f0. 0f6 [7:0] out6 control this register controls out6, and the bit assignments for this register are identical to register 0x0f0. 0f7 [7:0] out7 control this register controls out7, and the bit assignments for this register are identical to register 0x0f0. 0f8 [7:0] out8 control this register controls out8, and the bit assignments for this register are identical to register 0x0f0. 0f9 [7:0] out9 control this register controls out9, and the bit assignments for this register are identical to register 0x0f0. 0fa [7:0] out10 control this register controls out10, and the bit assignments for this register are identical to register 0x0f0 . 0fb [7:0] out11 control this register controls out11, and the bit assignments for this register are identical to register 0x0f0 . 0fc [7] csdld en out7 out7 is enabled only if csdld is high. [7] csdld signal out7 enable status 0 0 not affected by csdld signal (default). 1 0 asynchronous power-down. 1 1 asynchronously enable out7 if not powered down by other settings. to use this feature, the user must us e current source digital lock detect and set the enable ld pin comparator bit (0x01d[3]).
ad9520-5 rev. 0 | page 70 of 80 reg. addr (hex) bit(s) name description 0fc [6] csdld en out6 out6 is enabled only if csdld is high. setting is identical to register 0x0fc[7]. 0fc [5] csdld en out5 out5 is enabled only if csdld is high. setting is identical to register 0x0fc[7]. 0fc [4] csdld en out4 out4 is enabled only if csdld is high. setting is identical to register 0x0fc[7]. 0fc [3] csdld en out3 out3 is enabled only if csdld is high. setting is identical to register 0x0fc[7]. 0fc [2] csdld en out2 out2 is enabled only if csdld is high. setting is identical to register 0x0fc[7]. 0fc [1] csdld en out1 out1 is enabled only if csdld is high. setting is identical to register 0x0fc[7]. 0fc [0] csdld en out0 out0 is enabled only if csdld is high. setting is identical to register 0x0fc[7]. 0fd [3] csdld en out11 out11 is enabled only if csdld is high. se tting is identical to register 0x0fc[7]. 0fd [2] csdld en out10 out10 is enabled only if csdld is high. se tting is identical to register 0x0fc[7]. 0fd [1] csdld en out9 out9 is enabled only if csdld is high. setting is identical to register 0x0fc[7]. 0fd [0] csdld en out8 out8 is enabled only if csdld is high. setting is identical to register 0x0fc[7]. table 50. lvpecl channel dividers reg. addr (hex) bit(s) name description 190 [7:4] divider 0 low cycles number of clock cycles (minus 1) of the divi der input during which the divider output stays low. a value of 0x7 means the divider is low for eight input clock cy cles (default: 0x7). 190 [3:0] divider 0 high cycles number of clock cycles (minus 1) of the divi der input during which the divider output stays high. a value of 0x7 means that the divider is hi gh for eight input clock cycles (default: 0x7). 191 [7] divider 0 bypass bypasses and powers down the divider; routes in put to divider output. [7] = 0; use divider (default). [7] = 1; bypass divider. 191 [6] divider 0 ignore sync ignore sync. [6] = 0; obey chip-level sync signal (default). [6] = 1; ignore chip-level sync signal. 191 [5] divider 0 force high forces divider output to high. this requires that ignore sync also be set. [5] = 0; divider output forced to low (default). [5] = 1; divider output forced to high. 191 [4] divider 0 start high selects clock output to start high or start low. [4] = 0; start low (default). [4] = 1; start high. 191 [3:0] divider 0 phase offset phase offset (default: 0x0). 192 [2] channel 0 power-down channel 0 powers down. [2] = 0; normal operation (default). [2] = 1; powered down. (out0/ out0 , out1/ out1 , and out2/ out2 are put into safe power- down mode by setting this bit.) 192 [1] channel 0 direct-to-output connects out0, out1 , and out2 to divider 0 or directly to clk. [1] = 0; out0, out1, and out2 are connected to divider 0 (default). [1] = 1; if 0x1e1[0] = 0, the clk is routed directly to out0, out1, and out2. if 0x1e1[0] = 1, there is no effect. 192 [0] disable divider 0 dcc duty-cycle correction function. [0] = 0; enable duty-cycle correction (default). [0] = 1; disable duty-cycle correction.
ad9520-5 rev. 0 | page 71 of 80 reg. addr (hex) bit(s) name description 193 [7:4] divider 1 low cycles number of clock cycles (minus 1) of the divi der input during which the divider output stays low. a value of 0x3 means that the divider is low for four input clock cycles (default: 0x3). 193 [3:0] divider 1 high cycles number of clock cycles (minus 1) of the divi der input during which the divider output stays high. a value of 0x3 means that the divider is hi gh for four input clock cycles (default: 0x3). 194 [7] divider 1 bypass bypasses and powers down the divider; routes in put to divider output. [7] = 0; use divider (default). [7] = 1; bypass divider. 194 [6] divider 1 ignore sync ignore sync. [6] = 0; obey chip-level sync signal (default). [6] = 1; ignore chip-level sync signal. 194 [5] divider 1 force high forces divider output to high. this requires that ignore sync also be set. [5] = 0; divider output forced to low (default). [5] = 1; divider output forced to high. 194 [4] divider 1 start high selects clock output to start high or start low. [4] = 0; start low (default). [4] = 1; start high. 194 [3:0] divider 1 phase offset phase offset (default: 0x0). 195 [2] channel 1 power-down channel 1 powers down. [2] = 0; normal operation (default). [2] = 1; powered down. (out3/ out3 , out4/ out4 , and out5/ out5 are put into safe power- down mode by setting this bit.) 195 [1] channel 1 direct-to-output connects out3, out4 , and out5 to divider 1 or directly to clk. [1] = 0; out3, out4, and out5 are connected to divider 1 (default). [1] = 1; if 0x1e1[0] = 0, the clk is routed directly to out3, out4, and out5. if 0x1e1[0] = 1, there is no effect. 195 [0] disable divider 1 dcc duty-cycle correction function. [0] = 0; enable duty-cycle correction (default). [0] = 1; disable duty-cycle correction. 196 [7:4] divider 2 low cycles number of clock cycles (minus 1) of the divi der input during which the divider output stays low. a value of 0x1 means the divider is lo w for two input clock cycles (default: 0x1). 196 [3:0] divider 2 high cycles number of clock cycles (minus 1) of the divi der input during which the divider output stays high. a value of 0x1 means the divider is high for two input clock cy cles (default: 0x1). 197 [7] divider 2 bypass bypasses and powers down the divider; routes in put to divider output. [7] = 0; use divider (default). [7] = 1; bypass divider. 197 [6] divider 2 ignore sync ignore sync. [6] = 0; obey chip-level sync signal (default). [6] = 1; ignore chip-level sync signal. 197 [5] divider 2 force high forces divider output to high. this requires that ignore sync also be set. [5] = 0; divider output forced to low (default). [5] = 1; divider output forced to high. 197 [4] divider 2 start high selects clock output to start high or start low. [4] = 0; start low (default). [4] = 1; start high. 197 [3:0] divider 2 phase offset phase offset(default: 0x0).
ad9520-5 rev. 0 | page 72 of 80 reg. addr (hex) bit(s) name description 198 [2] channel 2 power-down channel 2 powers down. [2] = 0; normal operation (default). [2] = 1; powered down. (out6/ out6 , out7/ out7 , and out8/ out8 are put into safe power- down mode by setting this bit.) 198 [1] channel 2 direct-to-output connects out6, out7 , and out8 to divider 2 or directly to clk. [1] = 0; out6, out7, and out8 are connected to divider 2 (default). [1] = 1: if 0x1e1[0] = 0, the clk is routed directly to out6, out7, and out8. if 0x1e1[0] = 1, there is no effect. 198 [0] disable divider 2 dcc duty-cycle correction function. [0] = 0; enable duty-cycle correction (default). [0] = 1; disable duty-cycle correction. 199 [7:4] divider 3 low cycles number of clock cycles (minus 1) of the divi der input during which the divider output stays low. a value of 0x0 means that the divider is low for one input clock cycle (default: 0x0). 199 [3:0] divider 3 high cycles number of clock cycles (minus 1) of the divi der input during which the divider output stays high. a value of 0x0 means that the divider is high for one input clock cycle (default: 0x0). 19a [7] divider 3 bypass bypasses and powers down the divider; routes in put to divider output. [7] = 0; use divider (default). [7] = 1; bypass divider. 19a [6] divider 3 ignore sync ignore sync. [6] = 0; obey chip-level sync signal (default). [6] = 1; ignore chip-level sync signal. 19a [5] divider 3 force high forces divider output to hi gh. this requires that ignore sync also be set. [5] = 0; divider output forced to low (default). [5] = 1; divider output forced to high. 19a [4] divider 3 start high selects clock output to start high or start low. [4] = 0; start low (default). [4] = 1; start high. 19a [3:0] divider 3 phase offset phase offset (default: 0x0). 19b [2] channel 3 power-down channel 3 powers down. [2] = 0; normal operation (default). [2] = 1; powered down. (out9/ out9 , out10/ out10 , and out11/ out11 are put into safe power-down mode by setting this bit.) 19b [1] channel 3 direct-to-output connects out9, out 10, and out11 to divider 3 or directly to clk. [1] = 0; out9, out10, and out11 are connected to divider 3 (default). [1] = 1: if 0x1e1[0] = 0, the clk is routed directly to out9, out10, and out11. if 0x1e1[0] = 1, there is no effect. 19b [0] disable divider 3 dcc duty-cycle correction function. [0] = 0; enable duty-cycle correction (default). [0] = 1; disable duty-cycle correction.
ad9520-5 rev. 0 | page 73 of 80 table 51. vco divider and clk input reg. addr (hex) bit(s) name description 1e0 [2:0] vco divider [2] [1] [0] divide 0 0 0 2 (default) 0 0 1 3 0 1 0 4 0 1 1 5 1 0 0 6 1 0 1 output static 1 1 0 1 (bypass) 1 1 1 output static 1e1 [4] power-down clock input section powers down the clock in put section (including the clk buffer, vco divider, and clk tree ). [4] = 0; normal operation (default). [4] = 1; power down. 1e1 [0] bypass vco divider bypasses or uses the vco divider. [0] = 0; use the vco divider (default). [0] = 1; bypass the vco divider. table 52. system reg. addr (hex) bit(s) name description 230 [3] disable power-on sync power-on sync mode. used to disable the antiruntpulse circuitry. [3] = 0; enable the antiruntpulse circuitry (default). [3] = 1; disable the antiruntpulse circuitry. 230 [2] power-down sync powers down the sync function. [2] = 0; normal operation of the sync function (default). [2] = 1; power-down sync circuitry. 230 [1] power-down distribution reference powers down the reference for the distribution section. [1] = 0; normal operation of the refere nce for the distribution section (default). [1] = 1; powers down the reference for the distribution section. 230 [0] soft sync the soft sync bit works in the same way as the sync pin, except that the polarity of the bit is reversed; that is, a high level forces selected channels into a predetermined static state, and a 1-to-0 transition triggers a sync. [0] = 0; same as sync high. [0] = 1; same as sync low. table 53. update all registers reg. addr (hex) bit(s) name description 232 [0] io_update this bit must be set to 1 to transfer the contents of th e buffer registers into the active registers. this happens on the next sclk rising edge. this bit is self-clearin g; that is, it does not have to be set back to 0. [0] = 1 (self-clearing); update all active regi sters to the contents of the buffer registers.
ad9520-5 rev. 0 | page 74 of 80 table 54. eeprom buffer segment reg. addr (hex) bit(s) name description a00 to a16 [7:0] eeprom buffer segment register 1 to eeprom buffer segment register 23 the eeprom buffer segment section stores the starting address and number of bytes that are to be stored and read back to and from the eeprom. beca use the ad9520 register space is noncontiguous, the eeprom controller needs to know the starting address and number of bytes in the ad9520 register space to store and retrieve from the eeprom. in addi tion, there are special instructions for the eeprom controller, operational codes (that is, io_update and end-of-data) that are also stored in the eeprom buffer segment. the on-chip default setting of the eeprom buffer segment registers is designed such that all registers are transferred to/from the eeprom, and an io_update is issued after transfer. see the programming the eeprom buffer segment section for more information. table 55. eeprom control reg. addr (hex) bit(s) name description b00 [0] status_eeprom (read-only) this read-only register indicates the status of the data transferred between the eeprom and the buffer register bank during the writing and reading of the eepr om. this signal is also available at the status pin when 0x01d[7] is set. [0] = 0; data transfer is done. [0] = 1; data transfer is not done. b01 [0] eeprom data error (read-only) this read-only register indicates an error during th e data transferred between the eeprom and the buffer. [0] = 0; no error. data is correct. [0] = 1; incorrect data detected. b02 [1] soft_eeprom when the eeprom pin is tied low, setting soft_eeprom resets the ad9520 using the settings saved in eeprom. [1] = 1; soft reset with eeprom settings (self-clearing). b02 [0] enable eeprom write enables the user to write to the eeprom. [0] = 0; eeprom write protection is en abled. user cannot writ e to eeprom (default). [0] = 1; eeprom write protection is disabled. user can write to eeprom. b03 [0] reg2eeprom transfers data from the buff er register to the eep rom (self-clearing). [0] = 1; setting this bit initiates the data transfer from the buffer register to the eeprom (writing process); it is reset by the i2c master after the data transfer is done.
ad9520-5 rev. 0 | page 75 of 80 applications information frequency planning using the ad9520 the ad9520 is a highly flexible pll. when choosing the pll settings and version of the ad9520, the following guidelines should be kept in mind. the ad9520 has four frequency dividers: the reference (or r) divider, the feedback (or n) divider, the vco divider, and the channel divider. when trying to achieve a particularly difficult frequency divide ratio requiring a large amount of frequency division, some of the frequency division can be done by either the vco divider or the channel divider, thus allowing a higher phase detector frequency and more flexibility in choosing the loop bandwidth. choosing a nominal charge pump current in the middle of the allowable range as a starting point allows the designer to increase or decrease the charge pump current and, thus, allows the designer to fine-tune the pll loop bandwidth in either direction. adisimclk is a powerful pll modeling tool that can be downloaded from www.analog.com and is a very accurate tool for determining the optimal loop filter for a given application. using the ad9520 outputs for adc clock applications any high speed adc is extremely sensitive to the quality of the sampling clock of the ad9520. an adc can be thought of as a sampling mixer, and any noise, distortion, or time jitter on the clock is combined with the desired signal at the analog-to- digital output. clock integrity requirements scale with the analog input frequency and resolution, with higher analog input frequency applications at 14-bit resolution being the most stringent. the theoretical snr of an adc is limited by the adc resolution and the jitter on the sampling clock. considering an ideal adc of infinite resolution where the step size and quantization error can be ignored, the available snr can be expressed approximately by ? ? ? ? ? ? ? ? = j a tf snr 2 1 log20(db) where: f a is the highest analog frequency being digitized. t j is the rms jitter on the sampling clock. figure 57 shows the required sampling clock jitter as a function of the analog frequency and effective number of bits (enob). f a (mhz) snr (db) enob 10 1k 100 30 40 50 60 70 80 90 100 110 6 8 10 12 14 16 18 t j = 1 0 0 f s t j = 2 0 0 f s t j = 4 0 0 f s t j = 1 p s t j = 2 p s t j = 1 0 p s snr = 20log 1 2 ? f a t j 07239-044 figure 57. snr and enob vs. analog input frequency see the an-756 application note and the an-501 application note at www.analog.com . many high performance adcs feature differential clock inputs to simplify the task of providing the required low jitter clock on a noisy pcb. distributing a single-ended clock on a noisy pcb can result in coupled noise on the sampling clock. differential distribution has inherent common-mode rejection that can provide superior clock performance in a noisy environment. the differential lvpecl outputs of the ad9520 enable clock solutions that maximize converter snr performance. the input requirements of the adc (differential or single- ended, logic level termination) should be considered when selecting the best clocking/converter solution. lvpecl clock distribution the lvpecl outputs of the ad9520 provide the lowest jitter clock signals available from the ad9520. the lvpecl outputs (because they are open emitter) require a dc termination to bias the output transistors. the simplified equivalent circuit in figure 41 shows the lvpecl output stage. in most applications, a lvpecl far-end thevenin termination (see figure 58 ) or y-termination (see figure 59 ) is recommended. in both cases, v s of the receiving buffer should match vs_drv. if it does not match, ac coupling is recommended (see figure 60 ). lvpecl y-termination is an elegant termination scheme that uses the fewest components and offers both odd- and even-mode impedance matching. even-mode impedance matching is an important consideration for closely coupled transmission lines at high frequencies. its main drawback is that it offers limited flexibility for varying the drive strength of the emitter-follower lvpecl driver. this can be an important consideration when driving long trace lengths but is usually not an issue. in the case where vs_drv = 2.5 v, the 50 termination resistor connected to ground in figure 59 should be changed to 19 .
ad9520-5 rev. 0 | page 76 of 80 thevenin-equivalent termination uses a resistor network to provide 50 termination to a dc voltage that is below v ol of the lvpecl driver. in this case, vs_drv on the ad9520 should equal v s of the receiving buffer. although the resistor combination shown results in a dc bias point of vs_drv ? 2 v, the actual common-mode voltage is vs_drv ? 1.3 v because there is additional current flowing from the ad9520 lvpecl driver through the pull-down resistor. the circuit is identical for the case where vs_drv = 2.5 v, except that the pull-down resistor is 62.5 and the pull-up is 250 . vs_drv lvpecl 50? 50? single-ended (not coupled) v s v s_drv lvpecl 127? 127? 83? 83 ? 0 7239-045 figure 58. dc-coupled 3.3 v lvpecl far-end thevenin termination v s_drv lvpecl z 0 = 50 ? v s = vs_dr v lvpecl 50? 50 ? 50? z 0 = 50 ? 0 7239-047 figure 59. dc-coupled 3.3 v lvpecl y-termination v s_drv lvpecl 100 ? differential (coupled) transmission line v s lvpecl 100? 0.1nf 0.1nf 200 ? 200? 07239-046 figure 60. ac-coupled lvpecl with parallel transmission line cmos clock distribution the output drivers of the ad9520 can be configured as cmos drivers. when selected as a cmos driver, each output becomes a pair of cmos outputs, each of which can be individually turned on or off and set as inverting or noninverting. these outputs are 3.3 v or 2.5 v cmos compatible. however, every output driver (including the lvpecl drivers) must be run at either 2.5 v or 3.3 v. the user cannot mix and match 2.5 v and 3.3 v outputs. when single-ended cmos clocking is used, some of the following guidelines apply. point-to-point connections should be designed such that each driver has only one receiver, if possible. connecting outputs in this manner allows for simple termination schemes and minimizes ringing due to possible mismatched impedances on the output trace. series termination at the source is generally required to provide transmission line matching and/or to reduce current transients at the driver. the value of the resistor is dependent on the board design and timing requirements (typically 10 to 100 is used). cmos outputs are also limited in terms of the capacitive load or trace length that they can drive. typically, trace lengths less than 3 inches are recommended to preserve signal rise/fall times and signal integrity. cmos cmos 10? 60.4 ? (1.0 inch) microstrip 07239-076 figure 61. series termination of cmos output termination at the far end of the pcb trace is a second option. the cmos outputs of the ad9520 do not supply enough current to provide a full voltage swing with a low impedance resistive, far- end termination, as shown in figure 62 . the far-end termination network should match the pcb trace impedance and provide the desired switching point. the reduced signal swing may still meet receiver input requirements in some applications. this can be useful when driving long trace lengths on less critical nets. cmos cmos 10? 50? 100? 100? v s 0 7239-077 figure 62. cmos output wi th far-end termination because of the limitations of single-ended cmos clocking, consider using differential outputs when driving high speed signals over long traces. the ad9520 offers lvpecl outputs that are better suited for driving long traces where the inherent noise immunity of differential signaling provides superior performance for clocking converters.
ad9520-5 rev. 0 | page 77 of 80 outline dimensions compliant to jedec standards mo-220-vmmd-4 091707-c 6.35 6.20 sq 6.05 0.25 min top view 8.75 bsc sq 9.00 bsc sq 1 64 16 17 49 48 32 33 0.50 0.40 0.30 0.50 bsc 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 7.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max exposed pad (bottom view) seating plane pin 1 indicator pin 1 indicator 0.30 0.23 0.18 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 63. 64-lead lead frame chip scale package [lfcsp_vq] 9 mm 9 mm body, very thin quad cp-64-4 dimensions shown in millimeters ordering guide model temperature range package description package option ad9520-5bcpz 1 ?40c to +85c 64-lead lead frame chip scale package (lfcsp_vq) cp-64-4 ad9520-5bcpz-reel7 1 ?40c to +85c 64-lead lead frame chip scale package (lfcsp_vq) cp-64-4 ad9520-5/pcbz 1 evaluation board 1 z = rohs compliant part.
ad9520-5 rev. 0 | page 78 of 80 notes
ad9520-5 rev. 0 | page 79 of 80 notes
ad9520-5 rev. 0 | page 80 of 80 notes ?2008 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07239-0-10/08(0)

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